Peter Chou Email & Phone Number

台灣 Taiwan 新竹縣

1. Responsible for test development on Teradyne/Advantest platform.2. Responsible for GaN/SiC test development.3. Responsible for CIS test solution development.

台灣

1. Responsible for Taiwan operation for 5G infrastructure IC wafer test and FT back end engineering.2. Early engage in CP probe card and FT Hardware design and manufacturing with outsource vendor.3. ATE vendor and OSAT survey and evaluation.

Kaohsiung

1. Mobile Touch product test program development.2. Mobile Touch products production sustaining.3. Test platform conversion.

1. test and product operation.2. Module test and yield improvement for biometric products.3. coordinate NPI tasks to secure manufacturing flow and take ownership to drive product success.

1. Lead team of 16 persons support NPI/Sustaining in APK and subcons. 2: Define clear way of working in cross function teams. 3: Support test time reduction, drive test coverage improvement . 4: work with Global foundry for yield improvement, product qualification, bench verification.

1. Co-work with test service company-Faraday on E320 test platform and bring it to mass production.2. Communicate and coordinate with each function team( RD,DFT,QA,Assy) and subcon performance management.3. work with UMC for .11um process yield improvement.

Job content :  Interact with headquarter product / test engineering teams and subcons ( up to 8 ). New product Introduction and sustaining .  worked closely with tsmc team for 55nm yield improvement.Achievement :  Successfully increase FT yield of company top running chipset product from 60% to above 90% by co-working with headquarter within 2 months. Successfully introduce GPU product on new test platform ( Advantest T2000).  Successfully introduce direct docking for GPU product and solved test unstable issue.

Job content :  Baseband / Chipset multi-site test program development on Catalyst/Tiger/Quartet.  Continuous test and yield improvement.  Subcon management – ASET and SPIL . Achievement :  Successfully convert baseband IC from Quartet(Single site , 10.8sec) to Catalyst (Dual Sites,9.5 sec). Solved South bridge critical SATA issue to eliminate dispute between company and Loadboard vendor.  Successfully bring up chipset dual sites testing on UltraFLEX .

Job content :  Help customer develop test program on Teradyne platform . Support all of production issues. Conduct training class regarding Catalyst, uW6000, Flex, RF GEN4 and support design in projects.Achievement : Help customers solve numerous production issues. Build up personal test competence in ADC/DAC/RF/Teradyne platforms. Build up global vision in semiconductor field.

Job Content :  Handled delta-design handler for half of a year. Handle MCU products with OTP/EEPROM inside on S20 , J750 ,versa test. Co-work with cross-functional team to make sure smooth mass production. Achievement :  Successfully done cold temperature elimination for one MCU product by Shmoo/Pin margin characterization.