Peter Moyle Email & Phone Number

Redmond, Washington, US

DV Infrastructure contractorPorting System Verilog and Verilog code in a large project from one version UVM to another. Fixing build issues.

Austin, Texas, US

HW Validation - Code adaptation to perform measurement for power consumption, leakage, rise times, and ADC performance and taking actual measurements at corners. Environment is ARM SOC/Linux development.

Santa Clara, California, US

Performed Validation for GDDR and APU's used for XBOX and PlayStation. Performed debugging such as evaluation/observation of BIOS timing parameters, and temperature issues. Ran qualifications for different version APU's paired with different manufacturer DDR's at all corners.

Armonk, New York, NY, US

Porting low level C code, Perl test deployment code, and participating in triage team to debug regression fails in simulation and an new hardware.C porting was for PCIe DMA routines for P9. Much of it was Linux based that was ported to bare metal for P10. Modified and wrote some new routines in Perl and debugged and fixed some in Python.

Round Rock, Texas, US

10/19 - 02/20 Board design for Auscomm/Dell Alienware 11/16 - 9/19 Software Senior Principal Engineer - Diagnostics Development11/15 - 11/16 Solution Architect - Senior Consultant - contractorModified and debugged windows middleware and driver for Dell hardware diagnostics. - Added new module for battery analytics, worked w/ vendor and battery team on.

Cambridge, Cambs, GB

- formerly Sunrise Micro Devices (acquired 15 Apr 2015)Wrote and ported directed tests in C and debugged RTL using Cadence IncisiveWrote test benches in Verilog for Bluetooth/arm Cortex M0 asics.Wrote Verilog checkersDevised and wrote Verilog AXI\AHB interface widgets (aka Fake register) to allow automation of tests which previously required manual.

Development of micro-controller hardware and firmware. Mixed signal circuit design and debug for lighting controls.Upgraded ultrasonic/ir occupancy sensor code for new uC and completed to prototype test in under 2 wksDesigned firmware and hardware for client switches for plug and play lighting control network -designed coded and debugged rom boot loader.

San Jose, California, US

Developing Perl scripts for the deployment of 3rd party diagnostics. Validating and debugging, and assessing coverage those diags. Analyzing failures and assisting with root causing. Debug of of DDR and i2c subsystems. Testing and debug of 10gE and FibreChannel subsystems. Testing SAS and SATA arrays for data and power. Evaluation and deployment of test.

San Jose, California, US

Hardware platform verification and debugging. - verification for resets and voltage sequencing for all models of video teleconferencing platforms.Linux kernel configuration and driver debugging. Authored specialized user level driver to receive network characters and poke them into the receiving node's keyboard buffer (a remote ethernet keyboard.

Santa Clara, California, US

Writing and debugging directed tests in assembly language at architechtural and micro architectural levels. Put together test plans for Core and NB MCA and NB DDR. Core was a brand new core, so very little previous work was leverageable. Debugging was performed at the following levels:1) Nasm assembly language2) RTL - Verilog 3) Ucode4) C++ checkers.

Development of diagnostics, debug tools, and server motherboard bringupAuthored Linux driver based DDR memory test suite and PCIE diagCo-Developed Linux PPC SBC based Jtag debug system for AMD cpu's, featuring instruction cache loadable code, single stepping, IO and memory read/write and scriptable or compiled, cache, Jtag or mixed diags/debug sequences.

Santa Clara, California, US

Ee, Cs

Bach Of Ee, Electrical Eng