Peter Nowottnick Email & Phone Number

Paris, FR

Paris, Île-de-France, France

Responsible for the definition of the digital parts of mixed-signal IC's / SoC devices and/or blocks constituting itin relationship with customers, project managers, and designers.Participating in the debates on architectural choices for research versus product tradeoff and in the interest of continuous improvement of the design and design methods.

Meylan, France & Paris Area, France

Responsible for the specification of the IC / SoC devices and/or blocks constituting it(features, performance, verification methods by simulation and on silicon), in relationship with customers, project managers, and other designers.Vis-à-vis customers, being the technical guarantor of the performance of the circuit in accordance with the.

Paris Area, France / La Ciotat, France

Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory and Localization (RTIL) Systems. - Lead actively the definition and implementation of the RTIL infrastructure (hardware and firmware) as well as the software platform serving it.- Participate in architecture definition and testing of the system software.

Paris Area & La Ciotat, France

Responsible for the development and delivery of a RFID-based infrastructure for Real-Time Inventory (RTI) Systems. - Lead actively the definition and implementation of the RTI software platform as well as the infrastructure hardware and its interfaces to the standard software products.- Participate in architecture definition of the stardard software.

Paris Area, France

Embedded systems architecture (hardware and software) and design methodology for APR-based touch systems. Implementation of embedded solutions in APR and other touch technologies.Strong interaction between physics design team and platform implementation team. Performed all stages of embedded system development from conceptual design and architecture.

Paris Area, France

DSP and microprocessor expertise for touch solutions using APR (Acoustic Pulse Recognition) system "ReverSys".Specification and implementation of dedicated APR front-end firmware on Audio-DSP device. Interaction with design team of back-end processor system (embedded Linux-based) and physical design team.

Paris Area, France

Lead and actively participate in development of new generation of microprocessors for embedded digital imaging.Micro-architecture design and RTL implementation of a dedicated image processor for embedded application. Full validation of the design based on manually written and synthesized firmware running on the designed processor.

Paris Area, France

• Technical responsibility for VLSI/RTL design team.
• Architecture definition, specification, implementation, verification and support of modules in MP-SoC (Multiprocessor System-on-a-Chip) devices.
• Technical contact point for international customers.
• Investigation into advanced design methodology for MP-SoC.

Paris Area, France

Privately founded start-up project, seeking venture capital...• Technical leadership for VLSI/RTL design group "5 engineers"• Working on reconfigurability aspects of the product, system architecture and future extensions• Contribution to business plan and product definition

Paris Area, France

2001-2002: “Validation Technical Leader” and “Validation Team Manager”• Technical Leadership of telecom product validation group (9 engineers)• Definition and implementation of automatic test environment (entire validation system, test boards, and software)• Project planning and tracking of activities of the validation team (4 projects)• Delivered entire.

Paris Area, France

1998-1999: “Application Group Leader”:• Lead a group of 3 engineers working on functional hardware validation• Specification of test and evaluation boards; Technically responsible for subcontractors• Customer support (software development on SPARClet processors): Technical contact point for US customers; Link between FAEs and the Application Lab in France•.

Hamburg, Germany

• Delivered to a European research project (SMILE, part of ESPRIT/OMI): 1) Clock-tick precise, timing accurate C-module of the SPARC-CPU for the architectural simulator 2) Specification and implementation of the performance analysis tool “ASAP”• Doctoral Thesis - Research in performance evaluation of real-time computing systems and conceptual work on.

Braunschweig, Germany

• Development and improvement of a new design principle of fault tolerant integrated circuits with low overhead, called FBR (functional block redundancy).Co-holder of a patent.

Dr.-Ing. (Phd), Electrical Engineering, Computer Science

Title of Dissertation: "Ein Werkzeug zur Leistungsbewertung von Echtzeit-Rechensystemen" (in German)

Dipl.-Ing., Electrical Engineering, Microelectronics

Education record

Education record

Education record