Peter Shi Email & Phone Number

Very wide range of Semiconductor industry expertise on both advanced high performance SOI and advanced low power bulk Si CMOS: process integration development, device architecture design and electrical targeting, device simulation and modeling, process/device reliability assessment, process margin calculation, deign rule negotiation and validation, circuit design and simulation, design/process co-optimization, product yield analysis and enhancement, product FA and qualification, and product technical marketing.Extensive foundry support experience on DRC/LVS, Boolean & mask layer generation, design rule waiver request, and other PDK related issues.Thorough understanding of device physics, FEOL & BEOL process integration, test structure design, product yield and process control metrics, and DFM with over 7 years of semiconductor industry experience.Hands-on failure analysis experience/techniques, such as ABIST, light emission/timing analysis, hot spot, reverse engineering/defect detection, FIB/SEM/TEM. Deep understanding of reliability mechanism and model, such as EM, BTS/SM, BTI, HCI, and TDDB. Solid experience of NonFET devices (diode, fuse, resistor, capacitor, and inductor) integration/characterization, and their usage in different designs/products. Strong issue solving, design of experiment, data analysis, programming, and advanced process (TSUPREM), device (DEDICI), and circuit (Spice) simulation skills.Good communication and coordination skills through interaction with product, design, technology and manufacturing teams.

Listed skills include Cmos, Ic, Semiconductor Industry, Semiconductors, and 12 others.

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  The University Of Texas At Austin

  Electrical And Computer Engineering