Peter Meyer Email & Phone Number

Ottawa, On, Ca

Ottawa, Canada Area

Systems Engineering Manager within the Timing and Communications Group, responsible for new product definition (hardware, firmware & software), product architecture and technical marketing. Functional manager of the Systems Engineering team for the Timing & Communications Group. Entire technology portfolio covers discrete, semiconductor and embedded SoC solutions including product lines of oscillators (XTAL, MEMS, XO, VCXO, TCXO, OCXO), clock distribution (fan-out buffers, zero-delay buffers), clock generation (synthesis, frequency conversion, NCO), jitter attenuation and clock synchronization (SyncE, PTP, IEEE1588).Primary focus on technologies that enable the transfer of frequency, phase and time synchronization over packet networks (IEEE1588/PTP, IEEE802.1as/gPTP, NTP and RTP), through the physical layer (SyncE, T1/E1, BITS/SSU, 1PPS, IRIG) and/or wirelessly (GPS/GNSS).Representative and contributor to standard development organizations with responsibility for ITU-T (Study Group 15), IETF (TICTOC, NTP), IEEE-SA (1588, 802.1, TSN/AVB, Avnu), CableLabs (DOCSIS, R-DTI, MBH), SMPTE (TC-32NF) and AUTOSAR. Author and presenter of technical papers/presentations at industry conferences, including ISPCS, WSTS, ITSF and FTF.Experience in the application of clocking, timing & synchronization across a wide range of markets including Communications, Enterprise, Data Center, Industrial, Power, Automotive and Audio-Video Broadcast.

Ottawa, Canada Area

System Architect Manager within the Timing and Synchronization product group, responsible for new product definition (hardware & software), technical marketing and development of roadmaps. Primary focus on technologies that enable the transfer of frequency, phase and time synchronization over packet networks (IEEE1588/PTP, IEEE802.1as/gPTP, NTP and RTP). Responsibilities include as well traditional physical layer & alternative synchronization technologies (SyncE, OTN and GPS/GNSS).Representative and contributor to standard development organizations with responsibility for ITU-T (Study Group 15), IETF (TICTOC, NTP), IEEE (1588, 802.1, PES), MEF (MBH), CableLabs (DOCSIS, R-DTI, MBH) and SMPTE (TC-32NF). Author and presenter of technical papers/presentations at industry conferences, including ISPCS, WSTS, ITSF and FTF. Functional manager of the System Architect team for the Timing & Synchronization product group, covering the entire product & technology portfolio, including clock generation (synthesis, frequency conversion, jitter attenuation & NCO), clock distribution (fan-out buffers), clock synchronization and packet processing.

Ottawa, Canada Area

System Architect within the Timing and Synchronization product line, responsible for new product definition (hardware & software), technical marketing and development of semiconductor product roadmaps. Primary focus on technologies that enable the transfer of frequency, phase and time synchronization over packet networks (IEEE1588 / PTP, NTP, RTP, ToP, PWE3 and CESoP). Responsibilities include as well traditional physical layer & alternative synchronization technologies (Synchronous Ethernet / SyncE, OTN, SONET / SDH, PDH / T1 / E1, BITS / SSU, GPS / GNSS).Representative and contributor to standard development organizations with responsibility for ITU-T (Study Group 15), IETF (TICTOC, NTP), IEEE (1588, 802.1) and MEF (MBH). Author and presenter of technical papers/presentations at industry conferences, including ISPCS, WSTS, ITSF and FTF.

Ottawa, Canada Area

Factory Applications Engineer for semiconductor communications products used primarily in the access and metro network. Focused on products that enable the transition from TDM to Packet networks (PWE3, CESoP, IEEE 1588 / PTP, ToP, SyncE / G.8262), including digital PLLs (DPLL), analog PLLs (APLL) and software PLLs (SPLL).World-wide technical support of Field Applications Engineers (FAE) and direct support of Tier 1 customer base. Technical responsibility for both hardware components and associated software API/drivers. Generate technical articles, competitive analysis, technical seminars, technology training, application notes and software patches & enhancements. Provide on-site customer support through-out customer design cycle from the opportunity stage/architecture definition through to production.Author of technical articles covering circuit emulation and synchronization technology, published in technical magazines such as EETimes, ECN, CommsDesign.com, Lightwave, AnalogZone and TMCNet.com.Specialization in circuit emulation (CESoPSN & SAToP) and timing over packet technologies. Previous specialization in VoIP gateway and desktop phone products as well as ATM AAL1/AAL2 products.

Ottawa, Canada Area

Factory Applications Engineer for semiconductor telecom products used in PSTN access equipment or CPE such as PBX and DLC with POTS interfaces. Responsible for both analog and digital product lines including SLIC, DAA, COIC, CODEC, DTMF and TSI components.