Senior Design Engineer
San Francisco Bay Area
• Designed MH series of high performance PCS (MH1), UMTS (MH101, MH102) and Cellular band (MH203, MH205, MH201) MMIC mixers featuring high IIP3 (>32 dBm), low conversion loss (7.5-8.5 dB), good isolation and requiring no external components. • Led design team that successfully transferred the MH line of MMIC mixers (MH1A, MH103A, MH201A, MH203A, and MH205A) to an outside foundry. Mixer designs not only met but in most cases exceeded target specifications. Reduced mask cost by implementing common die plans. • Designed I/Q Demodulator block for a RFID reader chipset in a SiGe BiCMOS process. Responsible for design tradeoffs, performance validation and setting I/Q Demodulator block specifications based on system level requirements and initial design simulations. • Designed Rx section of quad band, low power Rx/Tx MMIC in a SiGe BiCMOS process. The Rx section consumed <45mW and was designed to cover 4 frequency bands between 120 MHz and 950 MHz.• Spearheaded project that investigated feasibility of using an outside foundry to fabricate passive components in support of company’s MCM products. Designed 90 degree hybrids, diplexers, power dividers, inductors and various baluns for the Cellular and PCS/UMTS/ISM bands. • Worked on the design of the high performance and highly successful HMJ7-1 CATV mixer specifically optimized to meet the demanding spur requirements of the CATV industry. • Designed baluns of various topologies and transformation ratios. MMIC baluns as well as baluns using cores were developed.• Developed a R&D converter test station that can measure conversion loss, IIP3, IIP2 and isolations (L-R, L-I, R-I) from 5MHz to 8GHz.• Managed, in addition to my primary role as circuit designer, the Semiconductor Design Engineering Laboratory at the Milpitas facility. Supervised up to 3 technicians and 2 assemblers. Increased productivity by creating dedicated measurement setups and by initiating programs to automate those test stations.
