Peter Mares Email & Phone Number

San Jose, CA

• Designed a high-efficiency multi-stage power amplifier for BTS small cell applications employing digital pre-distortion (DPD).
• Worked on a high-linearity multi-stage power amplifier for BTS small cell applications.
• Supervised, in addition to my primary role as circuit designer, the Design Engineering CAD group of 4 people and the Design Engineering Technician group of 7 people, allocating resources to various Design Engineering.

San Jose, CA

• Worked on a fully integrated, internally matched 5GHz WLAN front end module (FEM) consisting of a LNA with a LNA Bypass Switch and a SPDT Transmit / Receive (T/R) Switch optimized for high throughput 802.11ac devices.
• Expanded Error Vector Magnitude (EVM) measurement setup capability for 5GHz switch measurements, extending maximum power to >24dBm at which EVM noise floor is <1%, enabling significantly improved switch EVM.
• Designed a family of wideband, high-performance LNA gain block products: TQP3M9005: NF=0.8dB, OIP3=34dBm and Gain=15.3dB at 1.9GHz. TQP3M9006: NF=1.0dB, OIP3=38.5dBm and Gain=13.5dB at 1.9GHz. TQP3M9007: NF=1.3dB.
• Investigated performance tradeoffs of various output stage topologies, structures, and layouts for 2.4 GHz WLAN power amplifiers.
• Led project and contributed a design to the development of high performance mixers with integrated LO amplifiers (ML483 / ML485). Designed the ML485 a wide band, low current, high IIP3 fully integrated MMIC converter.
• Managed, in addition to my primary role as circuit designer, the Design Engineering CAD group of 4 people (4+ years) and the Design Engineering Technician group of up to 8 people (2+ years). Allocated CAD and.

San Francisco Bay Area

• Designed MH series of high performance PCS (MH1), UMTS (MH101, MH102) and Cellular band (MH203, MH205, MH201) MMIC mixers featuring high IIP3 (>32 dBm), low conversion loss (7.5-8.5 dB), good isolation and requiring no.
• Led design team that successfully transferred the MH line of MMIC mixers (MH1A, MH103A, MH201A, MH203A, and MH205A) to an outside foundry. Mixer designs not only met but in most cases exceeded target specifications..
• Designed I/Q Demodulator block for a RFID reader chipset in a SiGe BiCMOS process. Responsible for design tradeoffs, performance validation and setting I/Q Demodulator block specifications based on system level.
• Designed Rx section of quad band, low power Rx/Tx MMIC in a SiGe BiCMOS process. The Rx section consumed <45mW and was designed to cover 4 frequency bands between 120 MHz and 950 MHz.
• Spearheaded project that investigated feasibility of using an outside foundry to fabricate passive components in support of company’s MCM products. Designed 90 degree hybrids, diplexers, power dividers, inductors and.
• Worked on the design of the high performance and highly successful HMJ7-1 CATV mixer specifically optimized to meet the demanding spur requirements of the CATV industry.

Postdoctoral Fellow

Doctor Of Philosophy (Ph.D.)