Driving MeshBox technology deployment worldwide as a HyperMesh Connectivity solution.

Responsible for Technical Roadmap of MeshBox hardware, which supports SmartMesh blockchain and ecosystem partner protocol stacks.

Led technical solutions development for MeshBox Foundation.

• Addressed Digital-Signal-Processing (DSP) and Central-Processing-Unit (CPU) SoCs’ inefficiencies in terms of wasted cycles controlling data-movement and synchronization. - Specified Autonomic Transport circuitry (which offload DSP/CPUs), including Task Scheduler, Queue Management, Buffer Management, and Edge-Controller (2-sided Direct-Memory-Access (DMA) with multi-mode isolation) - Resulted in Message-Queuing and DMA improvements being incorporated into Huawei’s baseband SoCs (HiSDRv61xx).• Addressed Real-time Service-Level-Agreement (SLA) guarantees for 4th and 5th Generation Cellular, Cloud RAN and NFV, rather than relying on simulation - Scheduling of Task-Graphs (Directed-Acyclic-Graphs) with dependencies to compute Firm-Real-Time and Soft-Real-Time schedulability on Heterogeneous Multicore Platforms - Developed slack-based and latency-rate server schedulers for Many-Core systems, with multiple Clusters/Tiles - Developed hierarchical scheduler based on space-time regions representing resource pool (processors and memory) utilization to optimize for power utilization.• Addressed SoC Interconnect scalability and high latency issues due to only 68% efficiency from Head-of-Line blocking. - Led performance evaluation (including simulation) of several commercial NoCs for Huawei HiSilicon. - Proposed Clos-based NoC architecture which increased efficiency to 92% and resulted in NoC being included into Huawei SoCs (HiSDRv61xx)

• Spec-owner for next-gen Ethernet Switch SoCs (BCM 56843; 640 Tb/s) which is a part of Broacom’s 80% market penetration for Data-Center and Enterprise networks.• Participated in IEEE 802.1Q Ethernet standards including Qbb Priority Flow Control, Qau QCN Quantized Congestion Notification, and Qaz Enhanced Transmission Selection.• Defined requirements and features for Ethernet Switch debug, packet memory-management, queuing, and scheduling in order to optimize for throughput, latency, and lossless/lossy requirements.

• Led the Requirements and Architecture definition for next generation unified switch-fabric Application-Specific-Intergrated-Circuits (ASICs). Architecture addressed various network element requirements including Core, Edge, Aggregation, and Data-Center networks. Switch fabric is targeted for high-end, multi-chassis systems supporting 100+ Gb/s interfaces.• Developed Performance versus Cost quantitative metrics in order make architecture tradeoffdecisions.

• Developed Technology and Platform architectures for next-generation Multi-Core SoCs. Contributed to marketing efforts of SoC products for Access, Printing and Imaging, and Enterprise Routers with $1.2B in annual revenue. • Created and presented at Freescale Technology Forum: “Multi-Core Processor Interconnect Solutions” in 2007 and “Multi-Core Solutions and Applications” in 2008. • Specified requirements for Multi-Core SoCs targeting WCDMA and LTE eNodeB equipment. Determined mapping of baseband, L2, and Transport Protocols to QorIQ CPUs, hardware accelerators, datapath acceleration architecture, and memory sub-system.• Demonstrated how 3D-Integration of multi-die can increase margin by 11% and reduce manufacturing cost by 14% for the Multi-Core P4080 SoC.• Created SoC architecture addressing IPTV streaming media servers which includes networking, storage, and scheduling of Advertisement-Insertion.

• Wrote Product requirements for next generation P4080 Multi-Core SoC including Network Quality-of-Service, Platform (interconnect, memories, aggregators), and Datapath Acceleration logic.• Proposed System (Switch / Router) level flow control architecture in order to support Class-based and Virtual-output-Queuing flow control for I/O. Schemes increased throughput by 18% and 36% respectively.• Proposed improved multi-level queuing arbitration algorithm which results in linear bandwidth allocation with setting of weight parameters through hardware-friendly WFQ algorithm.• Proposed Memory Transaction queuing architecture for DDR Controller based on Banks, Pages, tRAS parameters in order to improve DDR throughput.• Developed Network on Chip architectures for next generation Many-Core SoCs.• Specified architecture for 6-level hierarchical WFQ traffic scheduler supporting 5 million flows as required by a Tier-1 Wireless equipment manufacturer.

• Developed marketing plan and technology roadmap for switch fabric and bridging ASSPs including product definition, strategic value proposition, and positioning.• Created and presented joint development project with LG Electronics (South Korea). Managed engineering team implementing a Switch Fabric chipset used in the Multi-Service-Router-40 deployed in Korean Telecom’s carrier networks.• Created and presented system architecture proposals to Tier-1 communications OEMs and TEMs to sell switch fabric products: Lucent, Alcatel, Nortel, Ericsson, Cisco, Huawei, ZTE, LGE, Samsung, NEC, Hitachi, Fujitsu, Alaxala, etc. • Created marketing strategy presentations for investors to raise $30M over a 7 year period.• Gave talks at various conferences and tradeshows including Linley Group, RapidIO Summit, Globecom, Bus and Board. Press tour for Xe Switch chipset resulted in Best Switch Fabric Award from Analog Zone in 2004.

• Generated technology portion of business development proposals which led to securing investment, partners, and design-wins with LG Electronics, NEC Electronics, Intel, Agere Systems, and Motorola (Cport).• Led Customer marketing targeting Tier-1 OEMs including Cisco, Nortel, Lucent, Alcatel, Ericsson, Huawei, ZTE, Beijing Capitel, and Samsung. • Wrote Statement of Work for Joint Development Contracts with LG Electronics and Electronics and Telecommunications Research Institute (ETRI) of South Korea. Contracts brought in over $6M for NRE design work.• Led Marketing Requirements Definition specification of Erlang’s ENET Se and Xe Terabit Switch Fabric and Traffic Management chipsets.

Coordinated the detailed specification and implementation of the ATM Switch Module (ASM) ASIC. Led implementation team in ASM development. Created Data Sheet to be released to customers.