Philip Fernandez Email & Phone Number

Santa Clara, California, US

• Provided high-quality technical support to Macnica Americas’ FAEs and customers throughout North America to help drive revenue. Focused on supporting multiple aspects of FPGA designs including device, design tools and.
• Maintained on-going searchable database for technical issues to facilitate knowledge-sharing across FAE team and presented to FAE team weekly on open issue status.
• Administered Macnica Americas’ compute servers including hardware/OS upgrades as needed, managing user accounts, installing EDA tools and licenses, creating automation scripts and writing how-to documentation for new.
• Collaborated with other Macnica Americas groups (Sales, Marketing, IP development) to meet business goals.

• Provided design software technical support for Altera customers throughout North America, working across organizations to resolve customer issues.
• Wrote and reviewed technical documentation for external website to enable customers to resolve issues quickly on their own.
• Coordinated with worldwide AE teams and engineering to test new software and provide feedback prior to production release.
• Led North American RSC design software team, creating training plans, managing tactical operations and mentoring junior team members. Collaborated with other RSC teams in North America and worldwide to improve customer.

Prepared designs for IBM ASIC design signoff, enabling customers to focus on design and verificationTasks included: synthesizing HDL; inserting I/O, clock, and testability logic; creating timing assertions; and working closely with vendor on placement and timing closure effortsDocumented procedures and created automation scripts

Armonk, New York, NY, US

Supported numerous customers designing IBM ASICs, helping ensure designs met signoff criteria and interfacing with layout engineers to achieve timing closureProvided technical support on various topics: design entry, memory selection, design-for-test, clock planning, I/O placement, static timing analysis, floorplanning, design optimization, timing closure.

San Jose, CA, US

Supported numerous customers design LSI Logic ASICs, helping ensure designs met signoff criteria and interfacing with layout engineers to achieve timing closureProvided technical support on various topics: design entry, memory selection, design-for-test, clock planning, I/O placement, static timing analysis, floorplanning, design optimization, timing.