Main activities:- MyoAlert, an electronic device to help disabled persons request help when traditional methods don't fit anymore- DV++, freelance activity to help squeeze out the last bugs of RTL design, when quality matters.

The organization brings coaching to whoever requests it, whatever their conditions or resources. Being volunteer, I grow the membership, proposing events and trainings for coaches in the South of France.

Just make it happen. - Invent the sensor to detect muscular contractions - Electronic schematic, PCB design, soldering and last minute fixing - Firmware, digital filtering, from embedded SW to HTML/CSS for hotspot configuration - Marketing / sales

Don't let your emotions limit your success !I develop a methodology - "Optimisez Vous" http://www.optimisezvous.com/ to overcome emotional hurdles. With subtle mix of personal awareness, fun, NLP tools and little actions, one can make the behavioral changes for long term.Main strengths: - Public speaking and impacting presentations - Shyness and social relations - Business development

Create the French Design Center and recruit the first team members.Main Challenge: Grow the verification mindset in IP teams, delivering RISC-V processor IPs. Raise quality of verification to deliver to highest standards.Mentor engineers to raise awareness on quality, and how rare some bugs are.Recruiting in Spain, France, Czech Republic, UK, Poland, from Junior to 20+ years experience.Share best practice toward verification methodologies, bringing shorter development time keeping best quality.- Author of blog articles, public speaker in conferences- Documentation templates, from verification plan to errata notice- Enhance bug tracking and customer response- Brough up dedicated team for formal testing.Drove different teams responsible for: - Deliver random program generator - Compute farm creation, job scheduling and monitoring - Maintain and extend internal RISC-V architectural compliance test suite - Develop accurate architectural checker - Creating multiported memory agents (AXI, AHB) - Various block level test benches (Coherent data cache, FPU, top level, MMU)

Develop electronic solutions for your needs.Founded to build and sell open source 3D printers, then focus or electronic solutions. - Systems for escape games (RFID sensors, Push-button locks, remote monitoring, …) - Multimedia for exhibition in museum - Home automation

2019 - 2020 Verification Lead for next M-Class CPU - Challenge is fast delivery of a new technology - Choose the best methodologies, plan activity, set up team and resources2017 - 2019 Unit Level Verification Architect. - Define methodologies to deliver faster the next generation A-class CPU. - Support team on transition of methodology. - Help transition to management for young leads - Chair on different internal verification related forums2018 Responsible for intern recruitment season. - Set up the team of 3 leads and 15+ enginer-recruiters. - Train recruitment skills and delegation. Follow progress within the short timeframe. - Coach new intern's managers. 14 interns recruited this year.2018 - … Machine Learning tools for improving the verification. - Experiment new algorithms to improve quality of constrain random generation. - Develop tools to automatically provide data and enhance model with Machine Learning team.

2016 - 2017 Cortex-M23 verification team member. - Assigned in the middle of the project to help recover delays in delivery. - Assess the current status of verification, change methodologies and priorities to help team deliver in time with the expected quality.2013 - 2016 Lead Memory System RIS tool development. - Prototype started in 2010. Now used by CPU teams in 3 design centers. - Ensure team growth, customer support, and feature development toward finding difficult bugs. - Enhance FPGA-oriented algorithm for faster verification. - Today one of the main Verification tool for all A class CPUs.2013-07 A17 maturity verification Lead - Handle teams in Bangalore, UK and France - Organize verification effort, track bugs and report progress.2013 Cortex-A12 Memory system test bench Lead - Define requirements for the 4-person team - Test bench improvements, new scenarios - Track and report team progress - Bug tracking and support

2011-2012 Cortex-A9 MPCore and Cortex-R7 maturity - Wrote enhanced test plans - Understand and track customer issues, - Reproduce failure, corrective actions, errata review - database management and releases.2010 Deploy validation tools on Cortex-A9 FPGA and silicon - Parallel test generation (on cluster), and execution on the target - Porting new stress tests on FPGA.2009 Cortex-R7 data side validation owner - Add new scenarios for ECC, split lock and real time verification - Install and deploy continuous integration tool Buildbot - Deploy and support regression and reporting tools.2008 Cortex-A9 MPCore L1 memory system testbench owner - Complete verification infrastructure, faster to reach corner cases, - Develop new tests and scenarios. - Code and functional coverage analysis. - Also used to validate PL310 r3p0 (L2 cache controller)2006 Cortex-A9 MPCore Load Store Unit RTL design - cycle accurate systemC model - RTL design, validation and synthesis - deploy Data Side multi unit test bench, improving existing BFMs, generators and checkers to support coherent multi-core CPU.2006 Creation of a new validation tool, generating random sequences of instructions. - Able to find unrevealed bugs on current and past products.2005 Cortex-R4 Bus Interface unit design and validation. - Cycle accurate model in systemC to evaluate performance, - RTL design of the bus interface unit, validation, performance and timing analysis. (verilog) - Block level L1 cache test bench design, including random stimuli generator, checkers, regression and tracking tools. (python)

The association bring coaching to whoever request it, whatever their conditions or resources.I have been president in 2018 of the south branch, growing the membership and proposing events for coaches and customers around Nice area.