Phillip Chang Email & Phone Number

Saratoga, California, Us

Zurich, Ch

• Developer for Digital Payload Processor (DPP), a R&D project for next-generation RF digital processing for communication satellites with Xilinx Ultrascale+ Processing Elements (PE) with direct RF sampling• Prototyped development on Xilinx VCU118 evaluation boards with ADI ADC/DAC FMC daughtercard with data transport using the JESD204B and Aurora SERDES protocols• Developed Weighted Overlap Add Filterbank FFT (WOLA-FFT) IP core for RF channelization that is scalable across filter sizes, oversampling rates, and FFT radixes• Developed reusable AXI bus framework with both Xilinx and in-house developed IP and Vivado TCL script functions for control over SmartLynq JTAG and LabView integration• Simulated IP with UVM-based verification environment with integration of C++ reference models• Architected RTG4-based Management Controller (MC) FPGA: 32-bit LEON-based SOC for PE configuration with SpaceWire Router and collaborated on service-based command handling software dev• Deployed and maintained Windows Server 2016 as office Active Directory domain controller and host for Bugzilla, Subversion, software licenses, and production build environment• Network administrator using Ubiquiti Unifi and Synology NAS equipment – including VPN setup and RADIUS authentication with AD DC• Representative to the Xilinx Radiation Test Consortium (XRTC) and Single Event Effects / Military and Aerospace Programmable Logic Devices (SEE/MAPLD) industry working groups

Bethesda, Md, Us

• Developer for Reconfigurable Advanced Mission Processor (RAMP) IRAD, which the core of the LM Digital Payload including flight insertion in the in-development JCSAT-17 satellite• Designer of RAMP Configuration Manager (RCM) FPGA that manages and configures the payload Xilinx-based processing FPGAs and configuration scrubbing via Xilinx SelectMAP• Designer of the RAMP SpaceWire Router FPGA for intra- and inter-board command and data connectivity• Developed RAMP SpaceWire IP library, including Remote Memory Access Protocol (RMAP) Target support and instantiable endpoints and routers• Deployed MIL-STD-1553B Ethernet Bridge unit and developed low level driver/utility for data bus test development and debugging• Architected a SOC design with a LEON3FT SPARC-V8-based microprocessor with AMBA bus components to showcase flexible applications of RAMP• Representative to the NSF Center for High-Performance Reconfigurable Computing (CHREC), a joint industry and academic research group• Certified Principle Engineer (CPE) Delegate for the Geostationary Lightning Mapper (GLM) FPGAs for the in-orbit Geostationary Operational Environmental Satellite (GOES-16)• Designer of the GLM SpaceWire Board FPGA – Mission data and telemetry manager and instrument housekeeping controller• Designer of the GLM ADC Board FPGAs – Mission data digitization and packetization • Designer of the GLM FPAA FPGA – Instrument CCD mission data controller• Performed an independent hardware-level verification for the Manchester encoding protocol utilized for command/telemetry and data transport between various GLM boards