Experience in the field of ASIC verification and software development · Experience in developing Hardware Verification Language (HVL) based constraint driven verification environment with UVM methodology and system verilog · Experience of writing functional coverage.· Understanding of bus protocols like Ethternet (PCS) ,APB, AXI3· Good skill on Test cases/Test bench component development including Constrained Random Stimulus Generators, Design Reference Model, Protocol Checkers, Sequences, Generic APIs, Coverage Models, Drivers and Monitors