(1). Giga-bit Ethernet PHY IP enhancement(2). G.Fast(ITU-T 9701) vectoring RTL design, FPGA/ASIC verification(3). G.Fast(ITU-T 9701) Retransmission RTL design, FPGA/ASIC verification(4). symbol alignment algorithm for G.fast CO-side(5). help chip timing closure including preparation of pre/post-CTS primetime script file, floorplanSkillsVerilog, LEC, Conformal-ECO, Simulink, primetime

(1). mobile phone/car use POWER IC control logic including power on sequence, DVS, state machine, ECO, FPGA emulation using altera cyclone III (2). power bank control logic, including LED flash, torch, battary measurement, digital filter for sigma-delta AD, efuse controller, state machine, FPGA emulation using altera cyclone III(3). Audio relative digital block including high performance audio DAC digital part, CORDIC, band-width extension, dynamic range extension, multiband DRC, I2S(4). boost converter architecture and digital design including safeguard, adaptive boost, feed-forward control, PI control, PSM

(1). ADSL G.INP type 1~4 study & debug (2). using 0-in CDC tool to check clock domain crossing synchronization (3). AFE-D sigma-delta modulator modification (3-order to 4-order) based on C++ code from algorithm team

(1). VDSL PMD function implemetation, including: FFT/IFFT, Digital Filter, DSTU, CP/CS windowing (2). PTM MAC layer implemetation, including: DMA interface, QoS (Leaky bucket), 64/65 HDLC encap/decap, G.998.2(G.BOND for PTM) hardware

(1). SD controller enhencement (2). Using Visual C++ to implement ISO 14496-2 (MPEG4) simple profile codec (3). Using Visual C++ to implement ISO 10918 (JPEG) baseline codec, including YUV 444, 422, 420, 411 in decoder and YUV 422 in encoder (4). Using matlab & verilog to design and simulate digital IF part in PHS RF low IF system, including decimator, SRRC filter, interpolator, RSSI, digital gain control, TX dc offset calibration, vco calibarion(5). Using matlab and verilog to simulate and implement radix-8 512/1024-point FFT/IFFT engine, including butterfly-unit, block floating point, twiddle factor control and memory address controlSkillsC++

(1). digital filter design (2). ADC/DAC calibration (3). Frac-N PLL simulation & digital designSkills1. matlab 2. simulink