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Piyush Agarwal Email & Phone Number
Principal Design Engineer
at
Cadence Design Systems
LinkedIn matched
✓ Verified August 2026
3 data sources
Profile completeness 86%
Current company
Role
Principal Design Engineer
Location
Hyderabad, Telangana, India
Company size
Who is Piyush Agarwal? Overview
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Quick answer
Piyush Agarwal is listed as Principal Design Engineer at Cadence Design Systems, a with 10387 employees, based in Hyderabad, Telangana, India. AeroLeads shows a matched LinkedIn profile for Piyush Agarwal.
Piyush Agarwal previously worked as Staff Engineer at Samsung Semiconductor and Analog Design Engineer at Texas Instruments. Piyush Agarwal holds Master Of Technology - Mtech, Microelectronics from Indian Institute Of Technology, Bombay.
Company email context
Email format at Cadence Design Systems
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Cadence Design Systems
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Profile bio
About Piyush Agarwal
Strengths: End-to-end product ownership, Quest to deliver state-of-the-art products, Working with cross-functional teams, Fast ramp-up of junior engineers, DocumentationProcess nodes experience: 18A-130nmNumber of tape-outs: 10Patent:- Adaptive frequency scheme to improve charge pump regulation system current and power efficiencies by 20%Leadership Roles:-• Samsung Semiconductor: Ramped-up 3 new hires to take IP ownership independently• Texas Instruments: Complete product ownership involving specification derivation, architecture feasibility, IP design closure and reviews, system level simulations and verification, spearheading layout and verification teams, and mentoring 2 new college recruits• Cirel Systems (now Micron Technology): Design Lead for Li-ion battery charger IC
Current workplace
Piyush Agarwal's current company
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Cadence Design Systems
5 roles
Piyush Agarwal work experience
A career timeline built from the work history available for this profile.
Principal Design Engineer
CurrentHigh-Speed DesignSerDes bias blocks: Architectural improvements to work with core devices in IO supply, removed legacy design redundancies, technical screening of 20+ candidates
Apr 2024 - Present
Staff Engineer
NAND Flash Design TeamPower-on sequence for memory chip:-Project roadmap....system level architecture diagram.......schematic design Low supply BGR & PTAT block design for Thermal Sensor Project:-Innovated start-up circuitry for Banba BandgapA new architecture implementation for PTAT voltage generation from Banba bandgapPatent:- Adaptive frequency scheme to improve charge pump regulation system current and power efficiencies at low loads
Oct 2022 - Jan 2024
Analog Design Engineer
Power Switch groupProduct:- Ideal diode controller with current monitoring functionalityComplete design ownership of an external gate Vgs comparator starting from spec definition, robust design implementation and top level logic implementationDesign ownership & closure including layout pathways for critical blocks in IC like Bandgap references, Current bias, EN pins interface block, OV/UV comparator & protection circuitry, Load current monitoring & warning, Fault assertComplete design of a thermal sensor with 1uA IQQ & 10C accuracy without bandgap availability Chip top simulations and reviews for various system test cases followed by transistor level debug and fix[Product webpage - https://www.ti.com/product/LM74910-Q1]
Jul 2021 - Oct 2022
Design Engineer
PMIC core blocks: Bandgap, Bandgap Reference, Comparators, LDOs (with different compensation schemes), Charge-pumpIC-specific blocks: Error Amp Integrator for buck regulator, Preamp for MEMS microphone, Thermal Shutdown Comparator, Li-ion battery charger
Jul 2018 - Jul 2021
Team & coworkers
Colleagues at Cadence Design Systems
Other employees you can reach at cadence.se. View company contacts for 10387 employees →
LB
Louise Barker Hewitt
Colleague at Cadence Design SystemsUnited Kingdom
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SM
Supria M
Colleague at Cadence Design SystemsHyderabad, Telangana, India
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LZ
Lisa Zhao
Colleague at Cadence Design SystemsShanghai, China
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GV
Gokul Vanan.K
Colleague at Cadence Design SystemsSalem, Tamil Nadu, India
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AA
Ashik Anuvar
Colleague at Cadence Design SystemsBengaluru, Karnataka, India
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RS
Rahul Shah
Colleague at Cadence Design SystemsAhmedabad, Gujarat, India
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JV
João Vicente Souto
Colleague at Cadence Design SystemsBelo Horizonte, Minas Gerais, Brazil
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SA
Shivangi Aggarwal
Colleague at Cadence Design SystemsDelhi, India
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SC
Sneha C
Colleague at Cadence Design SystemsGreater Chicago Area, United States
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SA
Saida Akhter
Colleague at Cadence Design SystemsPortland, Oregon, United States
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Louise Barker Hewitt
Colleague at Cadence Design SystemsUnited Kingdom
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SM
Supria M
Colleague at Cadence Design SystemsHyderabad, Telangana, India
View →
LZ
Lisa Zhao
Colleague at Cadence Design SystemsShanghai, China
View →
GV
Gokul Vanan.K
Colleague at Cadence Design SystemsSalem, Tamil Nadu, India
View →
AA
Ashik Anuvar
Colleague at Cadence Design SystemsBengaluru, Karnataka, India
View →
RS
Rahul Shah
Colleague at Cadence Design SystemsAhmedabad, Gujarat, India
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JV
João Vicente Souto
Colleague at Cadence Design SystemsBelo Horizonte, Minas Gerais, Brazil
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SA
Shivangi Aggarwal
Colleague at Cadence Design SystemsDelhi, India
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SC
Sneha C
Colleague at Cadence Design SystemsGreater Chicago Area, United States
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SA
Saida Akhter
Colleague at Cadence Design SystemsPortland, Oregon, United States
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2 education records
Piyush Agarwal education
Master Of Technology - Mtech, Microelectronics
Bachelor Of Engineering - Be, Instrumentation & Electronics
FAQ
Frequently asked questions about Piyush Agarwal
Quick answers generated from the profile data available on this page.
What company does Piyush Agarwal work for?
Piyush Agarwal works for Cadence Design Systems.
What is Piyush Agarwal's role at Cadence Design Systems?
Piyush Agarwal is listed as Principal Design Engineer at Cadence Design Systems.
Where is Piyush Agarwal based?
Piyush Agarwal is based in Hyderabad, Telangana, India while working with Cadence Design Systems.
What companies has Piyush Agarwal worked for?
Piyush Agarwal has worked for Cadence Design Systems, Samsung Semiconductor, Texas Instruments, and Micron Technology.
Who are Piyush Agarwal's colleagues at Cadence Design Systems?
Piyush Agarwal's colleagues at Cadence Design Systems include Louise Barker Hewitt, Supria M, Lisa Zhao, Gokul Vanan.K, and Ashik Anuvar.
How can I contact Piyush Agarwal?
You can use AeroLeads to view verified contact signals for Piyush Agarwal at Cadence Design Systems, including work email, phone, and LinkedIn data when available.
What schools did Piyush Agarwal attend?
Piyush Agarwal holds Master Of Technology - Mtech, Microelectronics from Indian Institute Of Technology, Bombay.
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