Pontus Pleven Email & Phone Number

Malmö, Skåne, Sverige

Pulsed Coherent radar digital controller Development• Application specific instruction and operation decoder-controller.• 2.5 GHz digital implementation and verification.• Muli clock system with multi asynchronous domains.• SOC with multi Risc-Vs.• Multi AHB/APB master slave constructs with multi clock dynamic switching.• Multi memory with multi clock dynamic switching.• Extreme unconventional Low power 2.5 GHz counter implementation.• Multi ADC controller and data processor.• Hardware pre-processing of arithmetic calculations.• Ping-pong continuous data streaming to/from single port memories.• Hardware internal debug feature by pinless approach operating at 2.5 GHz.• RTL Power optimization with Ansys Power Artist time based analysis.• CDC/RDC SpyGlass constructs.• SDC constructs and Genus flow.• GLS verification and debug.• GIT/Jenkins flow.• RTL design in SystemVerilog-Verilog.• Part of UPF development.• Part of DMS development.• Chip validation - preparations, test generation, lab execution and post verification.• Deep technical documentation and presentation.• Setup of office design specification in Latex.• Pre-study of next Chip generations.• Part of 2 major Chip generations.

Thalwil, Switzerland

GNSS Chip Development• Asic implementation of the World´s first on-chip GNSS jammer filter.• Asic implementation of GNSS chip power up-down-sequencer/controller.• Asic implementation of GNSS on-chip XTO calibration algorithm.• Asic implementation of GNSS chip pads.• Verification of GNSS acquistion HW engine - SystemC model vs HW implementation.• Verification of GNSS chip level with Software test cases.• Part of delivering RF IC.WiFi Chip Development• Asic methodology planning.• Generating/Integrating SOC RAMs.• Draft implementation of SOC system controller.LTE Chip Development• HW accelerator implementation of LTE - PSS algorithm.• SystemC/C++/VHDL methodology implementation.• HW accelerator implementation of LTE - SSS algorithm.

Lund, Sweden

Digital Modem Development• Implementing RTL for DL measurement filters in the Baseband IC.• Implementing HW accelerator IPs in RFIC for off-loading main CPU tasks.• Supporting RFIC SW for digital functionality.• Driving and implementing Ericsson’s first Baseband and RF IC, CPU-driven verification. Proving complete link and control functionality of HW and SW before tape-out of silicon.• Extreme SW debugging in HW simulation and lab silicon.• Implementing ARM AMBA 7 Gbps back-plane for next generation RF IC.• Part of delivering and supporting 5 generations of RF IC (+10 tape-outs).• Part of delivering and supporting 3 generations of Baseband IC's (+3 tape-outs).

Digital Modem Development• Project database responsible, EDA tool methodology responsible, RFIC DigRF responsible, ST bus interconnectivity development responsible, RFIC digital top chip system verification leader.• Working on parallel chips with co-designs in Japan and in France.• RFIC wake-up partner.• Digital verification and debugging of silicon RFIC.• Implementing C and assembler code for STxP70 CPU low level functions.• Verifying and debugging STxP70 CPU chip communication in RFIC system on RTL level.• Implementing assembler code for CoWare Processor Designer CPU.• Verifying and debugging of CoWare CPU functionality on RTL level.• Appointed interface between hardware and software in RFIC project.• Implementing MIPI - RF Front End controller.• System test implementation for co-verification with dual-core RFIC.

2-3G Multimode Single Chip Development• Starting up the first hardware development site outside the head quarter in Cambridge, United Kingdom.• Pioneering work with developing the first true mixed signal implementation and verification process within CSR. Implemented a digital AGC controlling the analogue receiver chain in a mixed mode environment.• Responsible for the digital implementation of the receiver chain between the analogue receiver and the digital modem. Covering functional blocks such as decimation filter, channel and interpolation filters, transmitter crosstalk estimation and cancellation, DC estimation and compensation, IQ mismatch alignment estimation and compensation, and frequency offset compensation blocks. Implemented floating point models and complying fix-point models in Matlab as references. Implemented digital Verilog fix-point versions of the Matlab models. Implemented test benches in Matlab, Verilog and SystemVerilog. Simulated and verified all models and implementations. Integrated the digital receiver chain into the digital module and verified functionality locally and on a high top level. Checked linting and executed basic synthesis. Wrote complete functional hardware implementation specification. Wrote software implementation guidelines.• Implemented HSIC PHY USB 2.0 device controller in Verilog with local test benches.• Local IS/IT responsible.

Lund, Skåne, Sverige

Bluetooth Digital Baseband IP Development• Responsible for the receiver chain in the Bluetooth baseband controller.• Implementing and upgrading the receiver RTL modules.• Simulating and verifying the implementation.• Implemented major changes to control the radio.• Main responsible for the information flow between the Baseband and Radio department.• Assisting the radio department with their digital blocks.• Assisting sales team with technical knowledge.• Assisting IP customers with IP training and IP start-ups.• Assisting IP customers with bug/metal fixing.• Project leader for converting a VHDL IP to a Verilog IP.• Implementing converting process and RTL updates to the Verilog IP.• Implementing the verification process for the Verilog IP.• Implemented parts of the receiver chain for Bluetooth High-Speed proposal.• Implemented high abstract layers with Cossap GUI and bit-true RTL.• Started a Bluetooth RF vendor program for external RF sources.• Implemented changes and additions to support multiple radio interfaces.• Verified implementation on FPGA platforms with five different radio vendors.• Updated firmware with support for new radio interfaces.• Extensive FPGA design debugging.• Accomplished to introduce Linux cluster for all Digital ASIC development.• Responsible for training of the Digital ASIC staff.• Responsible for CAD tools at the Bluetooth Digital ASIC department.• Beta tester for new CAD tool versions.• Selected to start up a new Digital Radio department.• Implemented parts of the receiver for Bluetooth Medium Rate Digital Radio.• Firmware implementation for the Digital Radio.• FPGA synthesis for the Digital Radio.• Extensive FPGA design debugging.

Bluetooth Digital Baseband Chipset DevelopmentInvolved in the front-back-end work of the SOC including tasks such as:• ASIC synthesis of the chip.• DFT work of the chip.• Static timing analysis of the chip.• Logical equivalence checking of the chip.• Pre- and post-layout simulation of the chip.• Chip simulation including the ARM cpu and firmware.• Involved in the work with the external silicon vendor VLSI.

Bluetooth Digital Baseband Chipset Development • Implemented RTL (VHDL) modules in the receiver path of the first Bluetooth Controller on silicon from Ericsson.• Implemented local test benches in VHDL with PERL regression scripting.• Simulation and verification of the receiver chain.• Basic synthesis of local modules for sign-off to back-end team.• Co-operation with the research department for developing new functionality.• Documentation of the receiver implementation.

Mba, Executive Master In Business And Administration

M.Sc.E.E., Electrical Engineering

U.D.E.E., Electrical Engineering