✦ Designed and developed an innovative VHDL-based hardware IP for Ultrasound ImageReconstruction in the Frequency-Domain, seamlessly integrated with Xilinx IP cores.✦ Successfully validated its functionality on the Xilinx FPGA UltraScale+ series with XilinxVivado, Matlab, and VHDL.✦ Achieved Ultrasound Image Reconstruction at over 1300 fps while conserving 5% of FPGAresources and 70% of FPGA memory resources.

● Design & Communication II (Spring 2023)● Microprocessor-Based Systems (Fall 2022)

✦ Contributed to designing and developing block tree quantization parameters (QP IP) for advanced video encoding codecs (AVC, HEVC, AV1) using SystemVerilog and Verilog.✦ Conducted firmware emulation and automated simulation Testbenches for QP IP using SystemVerilog, C, and Questa sim, resulting in a team time savings of over two months.✦ Achieved >5% video quality improvement (PSNR, SSIM).

✦ Computer ArithmeticA comprehensive study on imprecise arithmetic, non-conventional arithmetic, and high-precision arithmetic.Design hardware-friendly arithmetic algorithms targeting ASIC or FPGA platform.✦ Hardware AcceleratorDesigned hardware accelerators for Digital Signal Processing applications, including image and video processing and FIR Filtering, by employing imprecise and non-conventional arithmetic approaches, such as the Residue Number System (RNS) and Ternary Valued Logic (TVL).✦ FPGA & ASICImplemented proposed architectures using VHDL, TSMC libraries for ASIC (Synopsys compiler), and Xilinx Vivado for the FPGA platform.✦ Ternary Valued LogicDeveloped an innovative VHDL-based Ternary library for comparing and evaluating Ternary hardware designs, significantly accelerating the conduct of performance metrics for faster design efficiency assessments.

● Fundamentals of Computer & Programming(Winter 2021)● VHDL, Simulation & Synthesis(Fall 2020)● Fundamentals of Computer & Programming (Winter 2019)