Worked on Synopsys Lynx Flow (TSMC 12nm , 11 LM )Handled 2 blocks targeted at 1 GHz with Max Instance count of 2.3 MCompletely owned Synthesis , Floor planning ,Place & Route, Sign-off Timing ClosureImplemented floorplan experiments to get the better timing Developed floorplan and methodology using path groups to improve timingDeveloped place and route methodology to reduce Congestion, Cell density Drove Sign-off timing closure using PTSI and what-if analysisHandled challenges in fixing Power EM violationsAchieved DRC closure after implementing multiple top-level and functional ECOs

Worked as a Physical Design Engineer in Anubis Project.Tiles Statistics : Handled 4 tiles.,Having highest macros of 58 , 0.8M Instance count in sblk_mcb tile. Implemented with TSMC 16FF technology, 10 Metal layer process.Performed physical design activity starting from floor planning, placement, CTS and routing.Congestion is high because of feedthru. Created the placement bounds to achieve a better timingMain challenges faced to meet the timing in clock gating setup paths, and resolved congestion .Challenges faced while cleaning up DRC.Close the Timing in both Base and Metal ecos stages.TOOLS : Cadence EDI,Synopsys ICC compilers tools for PNR.PT for timing .Calibre for Physical Verification.

Handled 2 projects..Blocks Statistics : Handled 2 blocks (CMP &MJC ) .CMP block is a hierarchical having 3158 i/os, 140 macros ,1.19M instances with 2 voltage areas.Operating frequency is 450MHz. Implemented with tsmc 28nm technology, 7 Metal layer process.Performed physical design activity starting from floorplanning, placement, CTS and routing,. Main challenges faced to meet the timing between interfacing paths, and congestion issues due to heavy utilization. MJC block is having 1752 i/os, and 0.7M instances,104 macros ,Operating frequency is 600MHz. Implemented with TSMC 16FF technology, 8 Metal layer process.Having 2 power domains PD_TOP & PD_MJC.Floorplaning is critical due to criss cross connectivity of macros. Main challenge faced in Congestion reduction & meet the setup timing.

Worked on Intel RDT flow (TSMC 14nm , 14 LM)Handled 1 block targeted at 550 MHz with max instant count of 450KResponsible for Completely owned Floor planning ,Place & Route, Sign-off timing closure It is Bench marking project , done multiple iterations by changing the freq and vt type cells.Comparing the timing results ,utilization and instance count and DRCs in every stages and presenting results to the customer.Setting the PT and RTL Compiler Synthesis flows.