o 10+ years, 22+ projects, 5+ client exposure in DFT.o Executed/Lead /Managed teams on multiple projects, several tape-outs, pre-post Silicon debug and support from releases to productions ranging 5nm to 40nm technology node.o Developed young engineers in their careers to successfully take on high impact tasks and own significant portion of IC development.o Variety of product development experience delivering ASSPs for Consumer OIS camera, Healthcare Products, Processors, LTE Modem, Graphics and Throughput Computing Hardware Engineering (GTCHE).o Specialties in ATPG Coverage Analysis and Improvement, DRC Rule checks and fixes, LogicVision/Tessent MBIST Implementation, Pattern Generation, Validation and Simulation Debug, Pattern Handoff, pre-post Silicon Debug and Support, JTAG, iJTAG and S2P2 programming.o Resolute, efficient, accurate and dedicated to quality results.Workshops:DFT Compiler at Synopsys, Bangalore.Course content: DFT Compiler Flow, Creating Test Protocol, DRC Checks, DRC debugging using GUI mode(Design Vision), Top Down Scan Insertion, Multi-Mode DFT, DFT MAX for Scan Compression.Supervisor: Synopsys Team.TetraMAX1 at Synopsys, Bangalore.Course content: Stuck-at ATPG Flow, DRC Check, Debugging DRC Violations graphically, Writing and editing .spf file, Fault Classes, Writting Patterns in different format e.g. WGL, tdl, Binary, Pattern compression, TetraMAX diagnosis feature.Supervisor: Synopsys Team.TetraMAX2 at Synopsys, Bangalore.DSM(Deep-Submicron) or, at-speed or transition ATPG Flow, Power-aware ATPG, IDDQ Testing.Supervisor: Synopsys Team.