Pramod Balakavi work email
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Pramod Balakavi personal email
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Expertise:--------------• 22 years of ASIC/FPGA/System design experience at industry leading companies.• Held Technical/Managerial lead roles in challenging hardware design projects.• Technical leadership in all aspects of ASIC development with a proven track record of making largecomplex ASICs from Product definition to Production. Hands on experience in ASIC Architecture,Design, Verification and Silicon Debug.• Excellent experience with FPGA design and Xilinx P&R tools.• Excellent experience with Platform/System design and testing.• Familiar with networking and storage protocols and standards NVGRE, VXLAN, TCP/IP, Ethernet,FibreChannel, FCOE, NVME, SONET, OTN and DWDM.• Familiar with IO interface Protocols like PCIe, Interlaken, JESD204C, AMBA, AXI. • Awarded 12 Patents
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Soc ArchitectArmDublin, Ca, Us -
Technology Leader, Driving Next Generation Ai/Ml Soc Architecture And Development, Amazon DevicesAmazon Devices Jul 2021 - Dec 2024Technology Leader, SOC Architecture, Next Generation Al/ML SOC Development, Amazon Devices
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Technology Leader, System Architecture, Soc Architecture And Development, Project KuiperAmazon Jan 2020 - Sep 2021Seattle, Wa, Us* Member of Core Technical Leadership in defining overall Satellite Communications System architecture. * Played a key role in defining architecture of ASIC/SOCs being developed. -
Principal Soc ArchitectNvidia Dec 2017 - Dec 2019Santa Clara, Ca, Us* Responsible for driving Ethernet Architecture In Tegra SOC for ADAS platforms* Worked on architecture of 5G wireless infrastructure related IPs. -
Senior Principal EngineerVexata Inc Jun 2014 - Dec 2017* Worked on defining the system level architecture of Next Generation High Performance All Flash Storage Array VX-100F based on latest Enterprise SSD Drives and Intel Optane drives.* Participated in architecture and design implementation of Storage Processor FPGAs * Carried out Synthesis/P&R using Vivado 15.2/17.2 Tools. (Xilinx Virtex7 FPGAs)* Defined and implemented the system level verification environment by using System Verilog.* Worked on HW system validation by using various scripting tools like perl and python.* Worked on Performance and Benchmark testing of Vexata All Flash Array system by using Vdbench and FIO tools.
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Senior Principal EngineerBroadcom (Formerly Brocade Communications) Jun 2010 - Jun 2014• Technically Managed and participated in Architecture, Micro Architecture and implementation of next generation Low Latency Data Center 144x10GE/64x10GE ports Ethernet ASICs. • Responsible for the L2-L3 Switching/Routing Engine architecture and implementation.• Responsible for the verification strategy and reviewing test plans for the whole chip.• Worked with Marketing, Software and other cross functional teams in defining the features and functionality of next generation ASICs and corresponding Ethernet products.
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Senior Asic ArchitectBroadcom (Formerly Brocade Communications) Dec 2008 - Jun 2010• Managed and participated in Architecture, Micro Architecture and design implementation of next generation FibreChannel ASICs. • Worked with Cross functional teams in successfully delivery the Fibre Channel Products to Market.• Responsible for Port Logic, Routing, ACL and Queuing modules.* Delivered three generations of Fibre Channel Switch Chips ( 2G,4G,8G,16G)• Worked from architecture, micro architecture, implementation and synthesis across all the chips• Supported Software and Board teams in the Silicon debug activity
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Asic Design EngineerBroadcom (Formerly Brocade Communications) Jan 2006 - Dec 2008• Worked on defining the top level architecture and all the features of the two generations of HBA chips. • Worked on defining microarchitecuture and RTL implementation of port logic, Central Memory Module, Flash Interface and SMBUS• Managed and participated in the Silicon debug activity
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Asic EngineerCentillium Communications Jul 2001 - Oct 2002Us• Worked as a chip level verification lead for the next generation OC192 FEC processor. • Designed the Phase Shift/Async FIFOs, I2C, SPI and register interface modules. Integrated various loopback features of the chip into the design. Responsible for the overall Chip level integration
Pramod Balakavi Skills
Pramod Balakavi Education Details
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Indian Institute Of Technology, BombayElectrical Engineering -
University Of Hawaii At ManoaElectrical Engineering
Frequently Asked Questions about Pramod Balakavi
What company does Pramod Balakavi work for?
Pramod Balakavi works for Arm
What is Pramod Balakavi's role at the current company?
Pramod Balakavi's current role is SoC Architect.
What is Pramod Balakavi's email address?
Pramod Balakavi's email address is pb****@****zon.com
What schools did Pramod Balakavi attend?
Pramod Balakavi attended Indian Institute Of Technology, Bombay, University Of Hawaii At Manoa.
What skills is Pramod Balakavi known for?
Pramod Balakavi has skills like Fpga, Asic, Debugging, Rtl Design, Ethernet, Functional Verification, Soc, Static Timing Analysis, Ic, Verilog, Eda, I2c.
Who are Pramod Balakavi's colleagues?
Pramod Balakavi's colleagues are V J, Nikolinka Lazić, Rebecca Goh, Deepak Naik, Nancy Jen, Barry Dilly, Dipendra Rijal.
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