Pramod Balakavi Email & Phone Number

Dublin, Ca, Us

Technology Leader, SOC Architecture, Next Generation Al/ML SOC Development, Amazon Devices

Seattle, Wa, Us

* Member of Core Technical Leadership in defining overall Satellite Communications System architecture. * Played a key role in defining architecture of ASIC/SOCs being developed.

Santa Clara, Ca, Us

* Responsible for driving Ethernet Architecture In Tegra SOC for ADAS platforms* Worked on architecture of 5G wireless infrastructure related IPs.

* Worked on defining the system level architecture of Next Generation High Performance All Flash Storage Array VX-100F based on latest Enterprise SSD Drives and Intel Optane drives.* Participated in architecture and design implementation of Storage Processor FPGAs * Carried out Synthesis/P&R using Vivado 15.2/17.2 Tools. (Xilinx Virtex7 FPGAs)* Defined and implemented the system level verification environment by using System Verilog.* Worked on HW system validation by using various scripting tools like perl and python.* Worked on Performance and Benchmark testing of Vexata All Flash Array system by using Vdbench and FIO tools.

• Technically Managed and participated in Architecture, Micro Architecture and implementation of next generation Low Latency Data Center 144x10GE/64x10GE ports Ethernet ASICs. • Responsible for the L2-L3 Switching/Routing Engine architecture and implementation.• Responsible for the verification strategy and reviewing test plans for the whole chip.• Worked with Marketing, Software and other cross functional teams in defining the features and functionality of next generation ASICs and corresponding Ethernet products.

• Managed and participated in Architecture, Micro Architecture and design implementation of next generation FibreChannel ASICs. • Worked with Cross functional teams in successfully delivery the Fibre Channel Products to Market.• Responsible for Port Logic, Routing, ACL and Queuing modules.* Delivered three generations of Fibre Channel Switch Chips ( 2G,4G,8G,16G)• Worked from architecture, micro architecture, implementation and synthesis across all the chips• Supported Software and Board teams in the Silicon debug activity

• Worked on defining the top level architecture and all the features of the two generations of HBA chips. • Worked on defining microarchitecuture and RTL implementation of port logic, Central Memory Module, Flash Interface and SMBUS• Managed and participated in the Silicon debug activity

Us

• Worked as a chip level verification lead for the next generation OC192 FEC processor. • Designed the Phase Shift/Async FIFOs, I2C, SPI and register interface modules. Integrated various loopback features of the chip into the design. Responsible for the overall Chip level integration

Btech, Electrical Engineering

Ms, Electrical Engineering