Pranav Agarwal Email & Phone Number

San Francisco Bay Area

San Ramon, California, United States

Schenectady, New York

Brought unique capability of deep technical acumen combined with systems and product level thinking to drive direction of NTIs on multiple product platforms. Shaped controls and operability technology strategy and NTI roadmap for GE Onshore Wind. Led a horizontal team in loads and operability, consisting of engineering, global research and product line to.

Niskayuna

Technical and program leadership for $2M, 3-year program with a globally distributed team of 7 research scientists, developing control solutions to mitigate extreme and fatigue loads in turbine blades and tower, by developing algorithms utilizing new sensors in wind turbine. Developed technical solutions, mentored the team, performed sensor downselection.

* Technical Leader, Extreme Event Monitoring and Controls ProgramTechnical leadership for $1.65M program with a team of 7 research scientists in 3 continents. Architected and introduced two new concepts in wind turbine controls resulting in ~10% reduction in extreme loads on wind turbines. Developed technical solutions, mentored the team, scoped the IP.

* Model Based Controls Program (Individual Contributor)Identified a critical gap in wind turbine controls rooted in inherent coupling between rotor and tower dynamics. Leveraged theoretical constructs of multivariable controls to analyze the gap and design algorithm to reduce tower oscillations in a wind turbine. The algorithm is currently in production at.

Zürich Area, Switzerland

* Millipede – High density data storage Initiated and led collaboration between IBM Research Lab-Zurich and University of Minnesota to explore the application of high bandwidth detection algorithms to Millipede ultrahigh density (1 TB/inch^2) storage program at IBM Research Labs. Modality of bit read-write on polymer substrate forced a trade-off between.

* Designed and implemented digital signal processing blocks (interpolating filters and modulators) for sigma delta digital to analog convertors. * Experienced in entire digital design flow from front-end design in MATLAB to VHDL coding, synthesis, back end and test chip. * Identified opportunities, initiated and developed process improvements both in front.