Experienced IC Layout Engineer with a demonstrated history of working in leading foundry technologies. Skilled in tools like Cadence Virtuoso Schematic & Layout Editors, PVS, Assura, Mentor Graphics Calibre, Silicon Frontline R3D Simulator. Proficient in SKILL, Python, C++ & Verilog. Strong engineering professional with a Master's Degree focused in Integrated Circuit Design.Experience/Responsibilities: Driving/delivering top level integration & floorplan activities Leading a layout team and scheduling its activities through the project Execute Layout Reviews and create proper documentation Execute Tape Out procedures and task, support or drive Mask Orders submissions Cooperate with the development team on continuous improvement activities Prepare packaging technical drawings and support feasibility analysis Proficient in power, analog and mixed-signal layouts with experience in wide number of EDA tools Designing and delivering analog layout blocks with its floorplan strategy. Running all physical verifications as DRC/LVS/DFM and parasitic extractions to achieve high quality layout deliveries Layouts on numerous technologies across multiple device geometries, to include CMOS, BiCMOS, SiC, GaN Creation of transistor level sub block layout, based on schematics provided by designers (including careful analog considerations) Creation of state-of-the-art analog & mixed signal IC layouts Extensive knowledge of CMOS device operation  Knowledge on multiple EDA design environments and an ability to adapt to new design flows, processes and EDA tools.