Prashant Jaitly Email & Phone Number

Karnataka, India

Karnataka, India

San Jose, Ca, Us

Tool: Cadence Virtuoso(Schematic), Hspice,Finesim Worked on TX Design for 2000Mbps transmission DDR IO's. Blocks-TX Driver which supports both CTT/LVSTL termination. Predriver,Datapath and top level control logic design for DQ/DQS.Integration of top level DQ/DQS and running performance and functional sims for DQ/DQS.Working on low speed Failsafe 1.8V/3.3V I2C/I3C IO's with minimum fall time requirement for legacy I2C IO's.

Client: Western Digital: Tool: Cadence Virtuoso(Schematic), Hspice,Finesim Worked on TX Design for 1066Mbps transmission. Blocks-TX Driver which supports both CTT/LVSTL termination. Predriver,Datapath and top level control logic design for DQ/DQS.Integration of top level DQ/DQS and running performance and functional sims for DQ/DQS.

Bangalore, Karnataka, In

Design Experience1. Design of Bandgap reference (BGR) that operates on 1.8V voltage supply to generate a voltage reference of 1.2V with temperature variation of -40C to 125C for a maximum power consumption of 0.5mW and 100uA reference current in TSMC 28nm.2. Design of Low Dropout (LDO) that operates on 1.8V voltage supply to generate a voltage reference of 1.5V over a load current range of 100u to 10mA in TSMC 28nm.3. Design of two stage CMOS based Opamps that operates on 1.8V with an open loop gain of 65dB across all process corners and a phase margin of 55deg with a slew rate of 5V/us satisfying a CMRR of 40dB and a PSR of -5dB max till 1Mhz in TSMC 28nm.4. Design of various single stage amplifiers and current mirror architectures with a detailed AC and DC analysis of the same in TSMC 28nm. Client Based Project Experienceo Client-NXP Semiconductors(April 2018-Present) Project- Lynx46 12.5Gbps SerDes-TSMC 16nm Roles and Responsibilities: 1) Working on simulation and functional verification of blocks like Quadrature Generator,Phase Interpolator and Sampler for the high speed SerDes chip operating at 12.4416Ghz in TSMC 16nm. 2) Worked on system level simulation of LDO,BGR blocks for PON SerDes chip in TSMC 16nm. 3) Skilled with performing prelayout,postlayout netlist simulations after extraction,Monte Carlo Analysis,EMIR flow and SOA analysis. Client-NXP Semiconductors(January 2019-Nov 2019) Project- Lynx37 25Gbps SerDes-TSMC 16nm Roles and Responsibilities: 1) Worked on debugging Serdes Rx data path blocks like BLW correction and adaptive equalization for 16nm Serdes to meet the requirements. 2) Worked to introduce programmability in the constant-gm bias circuit of the Rx block of the 16nm Serdes chip. Client-Intel (September 2017- March,2018) Project- SerDes- Intel(10nm & 14nm) Roles and Responsibilities: 1) Understanding various verification flows and tool flows in Cadence Environment. Cadence virtuoso for schematic and ADE-L/XL for simulations.

Geneva, Switzerland, Ch

Worked as an analog design and verification intern in the ESD team at ST microelectronics in 28nm. My role was to study about ESD phenomenon and implement RC clamps and simulate testbenches for verifying the various protection circuits used.Daily Tasks included: Performing HBM,CDM checks on the protection circuits.Implementing RC filter circuit to detect the fast rising edge of the ESD event.

Noida, In

Completed 2 months summer training in Embedded Systems and Microcontrollers. I worked on Arduino boards and did few minor projects like Home automation,traffic light controller etc.

Master Of Technology - Mtech, Microelectronics

Bachelor Of Engineering - Be, Electronics And Communications Engineering

Education record