Pratik Wani Email and Phone Number

4 years of experience, as RTL Design Engineer in ASIC & FPGA domain.ASIC/IP/SOC Design and implementation of 7nm and 10nm technology. Experience in all type of the RTL developmentWorking on Front End VCLP and Power artist flow development and flow testing. Supporting different Business Units for setup and troubleshooting flow errors.Good Exposure on RTL coding, Clock Domain Crossing and Lint analysis and RTL Complier Tool. Run the complete FEBE flow: VCLP, Power artists, LEC, fishtail. Cheetah Flow: Enablement of tools, Run, debug, and fix the violation.