Prathamesh Save Email & Phone Number

San Jose, Ca, Us

Mountain View, Ca, Us

Focused on SoC Security Architecture and Virtualization.

Redmond, Washington, Us

Leading a team to deliver fabric infrastructure for SoC to support for ARM based AXI, AXI-Stream, APB, AHB, ATB, CTI protocols as well as transporting interrupts and telemetry messages.Micro-architected ARM CoreSight debug infrastructure for machine learning SoC. Worked with PD and timing teams to ensure correct placement of components on floorplan and timing closure.Micro-architected and designed logic analyzer IP used for tracing for the SoC.Micro-architected IP to help faster download of test images to SoC and same on tester time.Develop flow for SoC pad implementation.

San Diego, Ca, Us

Successfully taped out 7 chipsets intended for mobile, server and machine learning.Micro-architected ARM CoreSight based debug infrastructure for multiple SoC’s.Micro-architected global synchronization manager IP for machine learning chipset to synchronize PCIE DMA operations across multiple processing elements.Micro-architected and designed ATS (address translation services) logic as defined in PCIE Express Rev 4.0 specification.

San Diego, Ca, Us

Micro-architected and designed interconnects for server chips to support AHB/APB/ATB/CTI traffic. The component integration of interconnects using Tcl scripts in Magillem tool.Micro-architected and designed IP to support PMBus spec based AVS buses for server chips to communicate with off chip PMIC devices.Lead frontend team for Test Chip from frontend integration to post-silicon bring-up intended for testing custom memories and custom circuits. Collaborated with multiple teams with a tight schedule and limited resources to ensure a successful chip.

San Diego, Ca, Us

Micro-architected, designed and verified security IP for mobile chips to provide target end protection based on ARM based security groups. Verification was done on these IP in Vera language.Lead architecture and implementation of Memory BIST for mobile chips using Mentor Tessent tool. Worked on tools like Primetime for timing closure and Modelsim for gate-level timing simulations. Worked on post-silicon bring up and production vector generation.

San Diego, Ca, Us

Lead synthesis effort for sub-systems to be hardened in mobile chips. Along-with synthesis performed the responsibility of maintaining timing constraints, delivery of initial ETM models to chip level synthesis team, power analysis of netlist and delivery SDF files to verification teams to perform initial timing simulations.

San Diego, Ca, Us

Updation of tool flows developed for Spyglass and documentation.Worked on ENOVIA MatrixOne's DesignSync 5.0 for creating and updating modules.

M.S, Electrical Engineering

B.E, Electronics Engineering