Paul "Prem" Sobel Email & Phone Number

Austin, TX, US

• Software architect.
• Created Quantum Secure ASBE encryption algorithm which defeats statistical analysis and cryptanalysis.
• Developed security software with a focus on encryption/decryption products, including (>10) multifactor authentication and a C static library to automate enterprise pairwise communications.
• Developed encrypted USB software

Milpitas, CA, US

• Modify and design and create new functional tests written in C using tester API.
• Run functional tests on each firmware release. In case of failure add entry to bug database and gather data and help debug each failure with firmware team.
• Gathered coverage information on existing tests to design and implement test plan and tests for additional needed functional tests (written in C using tester API).
• Created and maintain web pages, available on Pliant intranet, to document testing procedures and other information needed by engineering team.

Santa Clara, California, US

• Fixed over 40 bugs in code base, found over 200 bugs in code base.
• Wrote thousands of new white code (C++) tests and diagnosed all failing tests
• Enhanced automatic test framework to: compare expected 2D image against actual.
• Use Klockwork for static code analysis to fix bugs, and BullseyeCoverage for unit tests to increase code coverage and eliminate bad coding practices

Arques, FR

• Actual company is different - was small British HW/SW IP company, URL is: http://arc.com/ - has since been acquired twice.
• Developed automated layout algorithm for HW and SW graph views of a design project in both C and Java to minimize line lengths and number of cross overs.
• Implemented a unit test regression system in C plus, perl, and shell scripts.
• Created and implemented automated testing methodology for existing and new CAD tools, including implementing over 70 automated tests for Debugger IDE. Also developed test strategy for new Eclipse based CAD tool for.
• Fixed Java and C bugs in Eclipsed based CAD tool.
• Evaluated and recommend various SW tools that were needed and worked with SW tool vendors on their bugs and new feature requests.

Palo Alto, CA, US

• Proposed new architectural directions for system and identified existing bad coding practices with recommendations for refactoring.
• Proposed systemic debugging infrastructure giving high visibility to system operation.
• Developed new algorithims to speed up and correct defects of system hash tables.
• Debugged and fixed many parts of the system.

US

• Wrote C library API functions for supporting real time multi-threaded embedded network security event correlation system using custom database with query API using 7 dimensional tree data structures for large >4GB.
• Contributing to architecture of network security Event Correlation System and Database with patent application.
• Implemented many code speed-ups and bug fixes in different parts of system.
• Helped in code reviews, setting coding standards, mentoring, recomending and installing purify and coverity.

• Developed software flow to: convert Agilent 93000 tester files to WGL; then convert WGL files to low cost HiLevel tester providing new capability for use in failure analysis including: GUI file viewers/editors and.
• Prepared and conducted requested tutorials to staff on: array, linked list, tree and graph data structures (especially in C), and image processing tutorials with a focus on noise removal and image enhancement.
• Wrote GDS2 (IC layout) file parser and tree data analyzer to save time for use by schematic generation support staff, plus GUI's for viewing several different format file contents.
• Consulted in design of Product Analysis Laboratory capability database, now used globally.
• Developed name space translator for FastScan and circuit name spaces; participated in the specification, design, coding, and testing of DFS (Diagnostic Fault Simulation) system using trees, graphs, and multidimensional.
• Supported Unix, and installed third-party CAD tools

• Fixed bugs and added features to new QT based GUI, all developed under Linux for Unix.
• Fixed bugs (improving success from 67% to 98%) and added the features for random loops and subroutines, to the random program generator product running under Linux or Unix.
• Developed hundreds of tests, for both the random program generator, and the new GUI.
• Conducted verification consulting to Obsidian Software customers in their new DSP, with functional coverage measurements, and discovered 187 bugs in customer systems.
• Rewrote MIPS exception handlers with an efficiency increase of 35% for size and speed.

• Developed a Microsoft Access-based medical application for lab results and diagnostic purposes with over 100 pages of VB code, and 40 sets of tables, forms, queries, and reports.
• Conducted requirements analysis with medical staff: physician, nurses, physical therapists, and clinical laboratory staff. Improved calculation efficiency from 30 minutes to three seconds.

• Upgraded MIPs simulator to support different derivatives or variations of MIPs core.
• Wrote random program generator for MIPs architecture which is used in conjunction with verilog model to generate many millions of instructions and combinations to test design to achieve design correctness on first.
• Enhanced the random program generator, adding many features for multiple MIPs cores, finding dozens of design flaws in each CPU.
• Developed X-Motif-based instruction set simulator and other tools in C for MIPs core project, all developed under HP AIX, and later, under Unix/Linux.
• Wrote test programs for MIPs core, in assembly language, and mentored other test development.
• Converted Verilog test bench for I2C into MIPs assembly language.

• Updated a Muse application, developed for the Navy, to have target-relative teleport, and enhanced GUI interface embedded in 3D space. Reduced learning time from two years to two months. System included the capability.
• Completed demo applications and documentation for the collision library.
• Developed a volumetric, iso-surface routine: wrote the program to write the program.
• Developed point cloud estimation routines.
• Developed system documentation and demonstration training programs.
• Developed a Muse application to view simulated air combat with interaction of ground-based facilities, including the means to filter out categories of objects, and a means to intelligently and dynamically subset what.

• Conducted computer science and electrical engineering courses, and research in mathematics.
• Managed, and contributed to, various university hardware and software projects: electric car electronics, and image processing of scanned images (photos and text).

Santa Clara, California, US

• Developed product planning and system architecture for 29K RISC processors
• Extended the 29K Architectural Simulator: added features and CPU variants. Simulator used to find customer's interrupt handler error.
• Contributed new patented features to 29050 architecture
• Reviewed new products from a systems viewpoint, conceived new product ideas; facilitated brainstorming
• Analyzed PAL design database to determine parameters & architectures for new families of programmable devices
• Developed algorithms for CAD software to support new programmable devices, made tradeoffs with actual device architecture, structure and parameters

• Contributed to the architecture and design of new mini supercomputer: Involved with hardware/software tradeoffs, contributed to software design environment, worked extensively on multi processor features, Developed.
• Worked as liason between hardware and software teams.
• Designed and wrote a cycle accurate architectural simulator for new computer, operating at the register transfer level with full details on the control logic: verified the new concepts, helped tune the architecture.

Falls Church, VA, US

• Project & Design Engineer for algorithm development of Automatic Target Recognizer: system design and developed the system simulator
• Redesigned the architecture & designed part of logic to fit a special purpose digital signal processor (less memory) into 2 gate arrays
• Guided other engineers also working on these chips
• Wrote a program of register level transfer model of the chips to generate test vectors
• Designed extensible high level language for and wrote an Image Processing Algorithm (Interpretive) Simulator – switching from Fortran to C
• Help designed architecture and algorithms for a multipurpose signal processor

Norwalk, Connecticut, US

• Helped define VLSI & system architecture requirements for Document Processor with graphics capability
• Helped develop logic design/architecture for Video Generation VLSI chip
• Wrote functional software simulator for Video Generation chip
• Created architectural design and specification for Cache & Bus Interface chip and for DRAM controller with ECC
• Developed an evaluation, study, and beta test of new internal CAD layout tool; includedng a layout of portion of the 16 bit cpu
• Conducted classes in tool use

• Designed minicomputer system: participated in CPU chip design, responsible for I/O Memory interrupt control chip design, virtual memory mapping chip design for 16/32 bit microprocessor chip set
• Wrote (and currently own) a program to reduce logic equations, achieving 40% reduction in a CPU control PLA
• Worked on team for new 32 bit products
• Initially participated in evolution and design of system architecture
• Developed CPU micro architecture and detailed design of pipeline logic
• Developed I/O subsystem design

• Conducted computer science and electrical engineering courses
• Installed minicomputer system
• Designed and implemented a Centronics printer interface and driver
• Conducted research in education.

• Participated in mission planning for Viking `75 and Mariner Venus Mercury `73 missions.
• Cognizant Engineer for Mariner Mars `71 flight computer software, plus member of mission design team. This included the design and implementation of a special purpose compiler for automatic inflight programming of the.
• Mariner Mars `69 Mission and design and flight operations team member (also participated in software design and implementation).
• I/O architecture and interface design for the STAR (Self testing & Repairing) computer; design and built several I/O interfaces.

Armonk, New York, NY, US

In the summer between my Bachelors and Masters degree, I determined the cause of an erroneous reed switch manufacturing test failure rejection rate of 40% that their senior engineers could not understand. This saved over $1,000,000 per year for over 10 years in rejected good reed switches.

M.S.E.E, Electrical Engineering

B.S.E.E, Electrcial Engineering