▪ Responsible for all aspects of Stuck-at-Fault and Transition-Delay Fault ATPG, Test Coverage Analysis, and Scan Gate-Level Simulation verification for leading DSP Processors using Mentor TestKompress and Synopsys VCS▪ Lead initiative to enable pattern retargeting of DSP core patterns to be used in SOC products▪ Lead overall Fault Grading Analysis of Memory BIST, Sleep/Retention, and Functional Tests for Test Coverage Improvement of DSP cores using Z01X fault simulator (Synopsys)▪ Used Static Timing Analysis in Primetime to debug timing violations observed in Gate-Level Simulations▪ Wrote DFT Architecture Specifications for multiple generations of DSP cores, as well as owned and maintained Timing Constraints, and GLS Simulation Requirements documentation▪ Generated and verified Logical-to-Physical Memory BIST address, data, and memory instance information to be used in manufacturing Failure Analysis for DSP cores with Custom and Compiler Memories▪ Owned and enhanced an automated flow for full regression testing of SAF/TDF ATPG and Scan Gate-Level simulations ▪ Lead initiative to enable the Mentor Veloce Hardware Accelerator to reduce CPU time for Scan SAF and TDF simulations▪ Scan Power Aware GLS verification▪ Conducted extensive verification and pattern optimization with custom On-Chip Clock Controller (OCC) of the DSP▪ Scan Insertion synthesis using Synopsys DFT Compiler

•Validated Design for Debug features on silicon including the ability to manipulate/stop the core clock mid execution as well as freezing and scanning out state of the flops•Wrote custom tool to extract DFD implementation from verification FSDB’s, generate CMM script stimulus to apply on System EVB and adhere to DAP Protocol•Brought features up across multiple testing platforms: System EVB via Lauterbach T32 Debugger, Advantest 93000,Inovys Personal Ocelot•Lead new innovative approach to identifying critical paths on DSP for functional tests•Wrote custom CMM scripts for T32 to validate critical DFD Security Fuse assignments•Took full ownership of Random Test methodology for the DSP on Silicon•Utilized the Raven Random Test generation tool from Obsidian (ARM) to generate random test stimulus•Fixed overlooked environment bugs causing non design compliant instruction sequences to be generated•Brought up a new in-house Random Test Generation flow for Silicon Validation•Created diversified templates to push limitations of the core and identify critical paths•Lab coordinator and headed efforts to add new organization and ESD compliance to the lab:Device inventory; Cataloged all stocked evaluation hardware; Coordinated full move of the lab with all systems moved and back online within 48 hours•Created new Shmoo Tool for System EVB to enable standardization between platforms•Wrote custom ARM code to interface DSP core based tests within a complex chip system•Enabled the Anritsu LTE Callbox to support the Modem team on all DSP enabled products•Identified Characterization set of DSP functional tests for new chipsets•Constructed 93k Test Programs to perform Fmax analysis and analyzed resulting data to identify top candidate Characterization tests•Performed First Silicon Bring-up and Characterization for DSP core on 65nm, 45nm, 28nm•Shmoo and Data collection for Fmax and Vmin across Process, Voltage, Temperature for DFT, Functional and Power Testing

•Development of test programs for SOC devices including baseband processors, application processors, multiple memories, and peripherals at both probe and final test, including 90nm and 65nm devices, and a 65nm test vehicle•Decrease cost through test time reduction and increase test yield at both wafer sort and final test•Wrote and developed test patterns in assembly, c, and verilog for verification and characterization of complex ARM, MCU, DSP and memory systems•Setup and developed complex files that work with existing company software to convert test patterns from a VCD (verilog core dump) to a BINL (tester formatted file) to be used for all work on the ATE•Development of test programs for the Max Frequency characterization of 90nm and 65nm device peripheral modules•Wrote extensive documentation of AC characterization methodologies for the Agilent/Verigy 93K platform•Developed and debugged BIST tests for the Virage Memories on a 65nm device including: memory validation, DVFS characterization, and memory repair•Developed and debugged power/current measurements tests: RUN IDD, WAIT IDD, STOP IDD; for 65nm devices•Learned about memory structure (translation tables, caches, etc) through the writing of the applications processor side of code for the Run IDD test on a 65nm test vehicle•Worked with and conducted experiments for design to help identify possible floating nodes and reasons for high leakage on DSM IDD tests for a 65nm test vehicle

•Created Microsoft Word template to standardize test planning for wireless baseband products in order to expand re-use capability between similar devices and increase productivity•Developed test requirements for wireless baseband peripherals•Researched the architecture and functionality of the USB On-The-Go module •Generated test plan document for the USB On-The-Go (USB 2.0 compliant) module emphasizing its overall functionality, AC characteristics, and modes of operation •Prepared a test coverage audit for a wireless dual core baseband processor