Develop company wide Product RoadmapProduct DefinitionChip SOC Definition and Architecture Leading the Product Modeling Platform Oversee 3rd Party IP managementAlign Cross functional and International Teams on Product Milestones and Engineering targets

Responsible for Micron's Internal SSD Controller Architecture Lead a team to define SSD controllers for Client OEM and Datacenter Cloud Segments  Set processes for successful multi-Functional teams engagement across international sites.  Worked with other functional members on exciting challenges of NVMe- SSD deployment for high end Enterprises . Worked on new products definition upcoming media technology like 3DX Point . Got Amazing opportunities to exercise tightly integrated working style across Design and Firmware Teams to enable working products with realistic schedules.

Tidal was one of the few Startups to adopt NVME Interface when the Standard was it in infancy. The company was acquired by Micron Semiconductor for multi million dollars for its First SSD Controller Silicon which it productized under the micron brand.  Founding Member  Early Product Marketing & Support for Business Development  Responsible for ASIC Architecture  Responsible for Product Modeling  Design Engineering

Delivered Multiple Product in - Client OEM value and High performance segments, - High Performance Enterprise as well as - Cost Sensitive Mobile-OEM Segments which needs low cost but high reliability.  Project Owner/Manager and Architect for the eMMC LDPC Nand Flash Controller ,  Responsible for customer engagement, early phase technical marketing and product definition. Product delivered innovative solution to the low power challenges of the product spec Involved in FW algorithm development including Flash layer Management, power interrupt scheme and workload dependent optimization.  Cross functional Team Leadership as product owner comprising team of 20 Engineers across Design, Verification, Firmware & ASIC P&R teams to meet aggressive schedule. Communication with Fab partner NEC and customer for pad, packaging and wafer probing schemes.

 Setup Platform Hardware and Software to enable On-Site Automated Flash Characterization  Customer interface for all NAND vendors including Samsung, Micron, Toshiba and Hynix Cycle through various conditions for Nand Devices to study Noise and Characteristic under various retention and endurance conditions. Assist the development and implementation of various DSP algorithms cater towards MLC and TLC Nand devices.

Technical Engineering Lead for eMMC BCH Nand Flash Controller (Link-A-Media Devices) 2007 – Apr 2011 Work with Micron Mobile eMMC Team as Flash Backend Technical Lead Hands on implementation of top level integration including Clock structure, ARM ,ONFI interface and eMMC Host interfaceHybrid SSD Controller, Nov 2010 – May 2011 The first Generation product is in mass production and the same SOC is reused for the second generation product due to the design ability to support new customer requests & Nand Features. Implemented BCH Decoder Design by Syndrome-BMA modules Driven the Analog team to support multiple vendor SI simulations and defined Spec for Nand IO.Enterprise SSD controller I and II , June 2008- Mar 2009 , Mar 2009-Nov 2009 Part of 3 person team to develop the Hardware and FW architecture to support Enterprise requirement of variable sector size leading to patent to support cross page management. Support production Qualification for both Enterprise controller.First Generation Client SSD Soc Controller , Mar 2008 – Nov 2008 Owner of multiple New Modules including company’s first SSD controller Nand Device Interface, First Channel Estimation block for soft information for LDPC decoder & Hardware Automation for Command Scheduling. Solely responsible for Micro-architecture, Implementation, verification, Timing closure, FPGA validation and Chip Bringup for above Modules.Software Experience : Developed Nand Flash layer Firmware functions for SSD SOC FW. Built initial development of the Verification environment and tester in C. Integrated the PCMCIA Card for T1/E1 Link to the Client and Server in C and ported the simulator system to linux platform

Masters Thesis focused on making ASIC Designs Robust against the presence of Silicon Defects.  Developed DFM (Design for Manufacturability) and DFY(Design for Yield ) Resilient standard cell suite from ground up .  Developed C Based Software Suite to parse through all the Standard Cell to Analyse Nodes and enable the STD Cell Development.  Worked in Magic, Setup Backend Tools Flow which involved research in itself for tool support from the world wide web to get the flow functional.Additional Research also done on Hardware Security and Trust.

 Developed Software application to integrate New PCMCIA Card into T1/E1 Link to the Client  Developed the Server application to enable handshaking and Network Protocol with the new Card  Additionally ported the simulator system to Linux platform. Exceeded expectations by completing the massive task within 3 months including the completely new Hardware - Software automated system.

In Charge of Two Wider Area LAN Networks.