Paul Mathison Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

Milpitas, California, Us

Developed compression and encryption acceleration drivers for PCIe device on Linux and FreeBSD, plus the tools to test them. Implemented L7 application identification prototypes on ARM processors with Snort and VPP.

Santa Clara, California, Us

Wrote dynamic protocol parsers for HTTP, HTML, and CSS, including URL rewrite as part of the new Clientless SSL VPN feature in PanOS firewalls. Analyzed LZMA compression and developed a new virus signature type for hash-based malware detection. Scaled zip and HTTP chunk decoding for high profile customers, fixing race conditions and introducing a hybrid software/hardware solution for zip. Designed and developed fast, flexible application id signature matching for better scaling of well-known L7 applications. Researched various regex technologies for possible inclusion in future products. Actively interviewed candidates for L7 dataplane team, and participated in college recruiting. Won third place in company hackathon for a new security feature, 2 patents in progress.

San Jose, Ca, Us

Integrated Akamai cache services into Cisco WAAS, through extensive collaboration with Akamai engineering. Designed and implemented a generic object cache for use by CIFS and HTTP, utilizing C and PostgreSQL for the backend metadata database. Created requirements and made key architecture decisions for a complete redesign of the CIFS/SMB application optimizer in C and C++. Implemented foundational data structures and algorithms for the new AO, including multi-thread-aware file tables and a hash-based cache, and prototyped an efficient protocol parser. Owned CIFS file preposition feature (Java), greatly improving scalability and stability through extensive design changes and intensive customer debugging. Trained and managed contract engineers assigned to CIFS.

San Jose, Ca, Us

Designed, developed, and owned the multi-threaded HTTP single-pass parser and analyzer in the data path on the IXP 2800 using Micro C including features: optimized regular expression analysis, dynamic header rewrite, cookie and URL hashing, UTF8 decoding and alarms, HTTP 1.1 persistence/pipelining, redirect, chunk encoded response, security alarms and logging, server connection reuse, unproxy/reproxy of connection, and virtualized statistics. Integrated HTTP data path with TCP/SSL, Load Balancer, App Inspect, and Connection Manager subsystems. Expanded feature set to become a generic L7 parser, supporting RDP, Radius, SIP, H.323, Skinny, and user-defined UDP and TCP based protocols for load balancing and application inspection (firewall). Oversaw design of HTTP compression and integration with AVS. Optimized and stabilized Load Balancer subsystem. Collaboratively designed other features for new product: role-based access control, configuration model, syslog, and IPC. Conducted new product introduction training to TAC, sales engineers, and marketing for the entire product. Visited customer sites. Mentored other engineers.

Wrote user configuration and monitoring command line interface for all features of the Content Switching Module. Integrated configuration model using EOBC IPC communication between Cisco Catalyst 6000 router (IOS) and CSM (VxWorks), maintaining mirror copies of config database and backwards / forwards compatibility. Designed and wrote multi-threaded socket-based HTTP server from scratch including digest authentication. Created XML configuration interface and associated DTD. Introduced Route Health Injection feature. Added support for concurrent CSM cards per router and concurrent config users per CSM, and integrated with new Cisco platforms. Trained TAC/escalation on config intricacies and provided customer support when needed. In the packet data path (IXP 1200), completed HTTP Cookie Insert feature. Collaborated on design of future features: SASP, device manager GUI, and fault tolerant config synchronization.

Developed the company’s primary test tool in MS Visual C++, used by development and manufacturing. Fine tuned image detection algorithms. Debugged low-level USB and RS232 protocol issues. Evaluated chip performance for new products.