Puneet Chauhan
AeroLeads people directory · profile

Puneet Chauhan Email & Phone Number

Sr. Principal Verification Engineer at SK hynix memory solutions inc.
Location: Santa Clara, California, United States 10 work roles 3 schools
1 work email found @skhms.com LinkedIn matched
✓ Verified July 2026 4 data sources Profile completeness 100%

Contact Signals · 1 work email

Work email p****@skhms.com
LinkedIn Profile matched
3 free lookups remaining · No credit card
Role
Sr. Principal Verification Engineer
Location
Santa Clara, California, United States
Company size

Who is Puneet Chauhan? Overview

A concise factual answer block for searchers comparing this professional profile.

Quick answer

Puneet Chauhan is listed as Sr. Principal Verification Engineer at SK hynix memory solutions inc., a with 257 employees, based in Santa Clara, California, United States. AeroLeads shows a work email signal at skhms.com and a matched LinkedIn profile for Puneet Chauhan.

Puneet Chauhan previously worked as Verification Architect at Altera Corp. (Aquired By Intel) and Performance Modeling Engineer at Futurewei Technologies. Puneet Chauhan holds M.Eng., Digital Communications And Dsp from Queen'S University.

Company email context

Email format at SK hynix memory solutions inc.

This section adds company-level context without repeating Puneet Chauhan's masked contact details.

{first}.{last}@skhms.com
89% confidence

AeroLeads found 1 current-domain work email signal for Puneet Chauhan. Compare company email patterns before reaching out.

Profile bio

About Puneet Chauhan

Experienced Professional in the area of Digital Design, Verification, Software and FPGA emulation.Experienced in managing both technical and schedule aspects of DV & Validation projects leading to successful delivery.Successfully Tapeout over 12 multi-million gate SOC ASICs with 1st Silicon success.In depth knowledge in Verification and ESL methodologies including VMM, OVM, UVM & TLM.Domain knowledge in Flash Storage, Networking, DSP, Video processing.Knowledge in following1) H/W & S/W Co-simulation - including Unix based Tool development2) FPGA Emulation - Dedicated FPGA, Palladium, Veloce3) Verification Methodologies - eRm, RVM, VMM, OVM, UVM3) DSP, channel shaping, QAM modulation, frequency shifters, FEC 4) Video Algorithms - JPEG2000, H.2645) Networking - Ethernet/VLAN, 1G, 10G, 40G, 100G.6) Interfaces - DDR2/DDR3, SATA, PCIe, SDIO7) Embedded Processors - Tensilica Xtensa, ARM R08) Bus protocols - AXI3/4, AHB

Listed skills include Asic, Soc, Functional Verification, Firmware, and 20 others.

Current workplace

Puneet Chauhan's current company

Company context helps verify the profile and gives searchers a useful next step.

SK hynix memory solutions inc.
Sk Hynix Memory Solutions Inc.
Sr. Principal Verification Engineer
Santa Clara, CA, US
Website
Employees
257
AeroLeads page
10 roles

Puneet Chauhan work experience

A career timeline built from the work history available for this profile.

Sr. Principal Verification Engineer

San Jose, Ca, Us

SystemVerliog and UVM training to jumpstart SOC DV team into Coverage & Assertion based methodology.Verification of NAND Flash controllers for SSD storage devices.Responsible for block and system level verification of NAND Flash Controllers for Read & Writepath including LDPC encoder/decoders.Worked on Resource Management of NVMe Host (PCIe side) commands.

Verification Architect

Altera Corp. (Aquired By Intel)

Verification Lead for Cable Modem upstream PHY ASIC. Delivered end-to-end upstream golden model in Matlab for vector comparison.Verification of the FEC block and fullchip verification.Build team of 5 DV engineers for end-to-end full-chip verification.

Jan 2013 - Dec 2014

Performance Modeling Engineer

Santa Clara, California, Us

ESL modelling of multicore SOC for 2G, 3G, 4G Software defined Radio using SystemC and TLM2.Performance modelling of multi-layered multiway associative L3 Cache Memory System for multicore DSP.

Jan 2011 - Dec 2013

Asic Verification Manager

Nethra Imaging (Aquired By Imagination)

Led a team of 25+ engineers for the verification of Video processing chipsetwith SATA storage interface. SOC interfaces included PCIe, XGMII, SDIO, Ethernet and othersSuccessfully introduced OVM verification methodology into the team.Worked with Cadence to integrate OVM testbench with Palladium hardware acceleration platform for H.264 Encoder/Decoder.

Mar 2009 - Dec 2010

Asic Verification Manager

Tzero Technologies (Company Closed)

Verification of PHY and MAC subsystems of Ultra-Wideband wireless modem.Designed testbench using OVM for UWB MAC subsystem.

Apr 2008 - Feb 2009

Principal Engineer, Verification Lead

Led the verification of FCoE subsystem using using SystemVerilog based Synopsys VMM.

Apr 2007 - Apr 2008

Senior Staff Engineer, Lead Verification/Validation

Idt (Acquired By Renesas)

Lead the Verification and then Validation of Serial Rapid IO switch ASIC using Synopsys RVM.

Jul 2005 - Mar 2007

Full Chip Lead For Verification & Validation

Shelton, Ct, Us

Owned the Full Verification responsibilities for SOC ASICs from Spec to Bringup of many multi-million gate SOC ASICs in the Area of ADSL/VDSL and VLAN networking.Lead Verification from Spec to Tapeout for multiple ADSL, VDSL devicesWorked on Bringup and Customer support for Post Silicon.Introduced Specman e to the Verification teams.Led the legacy C/C++ testbench conversion to eRM methodology.

Dec 1999 - Jul 2005
Team & coworkers

Colleagues at SK hynix memory solutions inc.

Other employees you can reach at skhms.com. View company contacts for 257 employees →

3 education records

Puneet Chauhan education

M.Eng., Digital Communications And Dsp

Queen'S University

B.Tech, Electronics & Communications Eng

Indian Institute Of Technology, Madras

High School Diploma, Science And Mathematics

Kendriya Vidyalaya
FAQ

Frequently asked questions about Puneet Chauhan

Quick answers generated from the profile data available on this page.

What company does Puneet Chauhan work for?

Puneet Chauhan works for SK hynix memory solutions inc..

What is Puneet Chauhan's role at SK hynix memory solutions inc.?

Puneet Chauhan is listed as Sr. Principal Verification Engineer at SK hynix memory solutions inc..

What is Puneet Chauhan's email address?

AeroLeads has found 1 work email signal at @skhms.com for Puneet Chauhan at SK hynix memory solutions inc..

Where is Puneet Chauhan based?

Puneet Chauhan is based in Santa Clara, California, United States while working with SK hynix memory solutions inc..

What companies has Puneet Chauhan worked for?

Puneet Chauhan has worked for Sk Hynix Memory Solutions Inc., Altera Corp. (Aquired By Intel), Futurewei Technologies, Nethra Imaging (Aquired By Imagination), and Tzero Technologies (Company Closed).

Who are Puneet Chauhan's colleagues at SK hynix memory solutions inc.?

Puneet Chauhan's colleagues at SK hynix memory solutions inc. include Chenrong Xiong, Troyal Brooks, James Jung, Jennifer Lee, and Wenwen Huang.

How can I contact Puneet Chauhan?

You can use AeroLeads to view verified contact signals for Puneet Chauhan at SK hynix memory solutions inc., including work email, phone, and LinkedIn data when available.

What schools did Puneet Chauhan attend?

Puneet Chauhan holds M.Eng., Digital Communications And Dsp from Queen'S University.

What skills is Puneet Chauhan known for?

Puneet Chauhan is listed with skills including Asic, Soc, Functional Verification, Firmware, Verilog, Debugging, Embedded Systems, and Systemverilog.

Find 750M verified contacts

Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.