Puneet Chauhan Email and Phone Number
Puneet Chauhan work email
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Puneet Chauhan personal email
Experienced Professional in the area of Digital Design, Verification, Software and FPGA emulation.Experienced in managing both technical and schedule aspects of DV & Validation projects leading to successful delivery.Successfully Tapeout over 12 multi-million gate SOC ASICs with 1st Silicon success.In depth knowledge in Verification and ESL methodologies including VMM, OVM, UVM & TLM.Domain knowledge in Flash Storage, Networking, DSP, Video processing.Knowledge in following1) H/W & S/W Co-simulation - including Unix based Tool development2) FPGA Emulation - Dedicated FPGA, Palladium, Veloce3) Verification Methodologies - eRm, RVM, VMM, OVM, UVM3) DSP, channel shaping, QAM modulation, frequency shifters, FEC 4) Video Algorithms - JPEG2000, H.2645) Networking - Ethernet/VLAN, 1G, 10G, 40G, 100G.6) Interfaces - DDR2/DDR3, SATA, PCIe, SDIO7) Embedded Processors - Tensilica Xtensa, ARM R08) Bus protocols - AXI3/4, AHB
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Sk Hynix Memory Solutions Inc.Santa Clara, Ca, Us -
Sr. Principal Verification EngineerSk Hynix Memory Solutions Inc. Dec 2014 - PresentSan Jose, Ca, UsSystemVerliog and UVM training to jumpstart SOC DV team into Coverage & Assertion based methodology.Verification of NAND Flash controllers for SSD storage devices.Responsible for block and system level verification of NAND Flash Controllers for Read & Writepath including LDPC encoder/decoders.Worked on Resource Management of NVMe Host (PCIe side) commands.
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Verification ArchitectAltera Corp. (Aquired By Intel) Jan 2013 - Dec 2014Verification Lead for Cable Modem upstream PHY ASIC. Delivered end-to-end upstream golden model in Matlab for vector comparison.Verification of the FEC block and fullchip verification.Build team of 5 DV engineers for end-to-end full-chip verification.
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Performance Modeling EngineerFuturewei Technologies Jan 2011 - Dec 2013Santa Clara, California, UsESL modelling of multicore SOC for 2G, 3G, 4G Software defined Radio using SystemC and TLM2.Performance modelling of multi-layered multiway associative L3 Cache Memory System for multicore DSP. -
Asic Verification ManagerNethra Imaging (Aquired By Imagination) Mar 2009 - Dec 2010Led a team of 25+ engineers for the verification of Video processing chipsetwith SATA storage interface. SOC interfaces included PCIe, XGMII, SDIO, Ethernet and othersSuccessfully introduced OVM verification methodology into the team.Worked with Cadence to integrate OVM testbench with Palladium hardware acceleration platform for H.264 Encoder/Decoder.
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Asic Verification ManagerTzero Technologies (Company Closed) Apr 2008 - Feb 2009Verification of PHY and MAC subsystems of Ultra-Wideband wireless modem.Designed testbench using OVM for UWB MAC subsystem.
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Principal Engineer, Verification LeadEmulex Corporation Apr 2007 - Apr 2008Led the verification of FCoE subsystem using using SystemVerilog based Synopsys VMM. -
Senior Staff Engineer, Lead Verification/ValidationIdt (Acquired By Renesas) Jul 2005 - Mar 2007Lead the Verification and then Validation of Serial Rapid IO switch ASIC using Synopsys RVM.
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Full Chip Lead For Verification & ValidationTranswitch Corp. Dec 1999 - Jul 2005Shelton, Ct, UsOwned the Full Verification responsibilities for SOC ASICs from Spec to Bringup of many multi-million gate SOC ASICs in the Area of ADSL/VDSL and VLAN networking.Lead Verification from Spec to Tapeout for multiple ADSL, VDSL devicesWorked on Bringup and Customer support for Post Silicon.Introduced Specman e to the Verification teams.Led the legacy C/C++ testbench conversion to eRM methodology.
Puneet Chauhan Skills
Puneet Chauhan Education Details
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Queen'S UniversityDigital Communications And Dsp -
Indian Institute Of Technology, MadrasElectronics & Communications Eng
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Kendriya VidyalayaScience And Mathematics
Frequently Asked Questions about Puneet Chauhan
What company does Puneet Chauhan work for?
Puneet Chauhan works for Sk Hynix Memory Solutions Inc.
What is Puneet Chauhan's role at the current company?
Puneet Chauhan's current role is Verification Expert.
What is Puneet Chauhan's email address?
Puneet Chauhan's email address is pu****@****bal.net
What schools did Puneet Chauhan attend?
Puneet Chauhan attended Queen's University, Indian Institute Of Technology, Madras, Kendriya Vidyalaya.
What skills is Puneet Chauhan known for?
Puneet Chauhan has skills like Asic, Soc, Functional Verification, Firmware, Verilog, Debugging, Embedded Systems, Systemverilog, Arm, Rtl Design, System On A Chip, Digital Signal Processors.
Who are Puneet Chauhan's colleagues?
Puneet Chauhan's colleagues are Julia Song, Ambrish Melkeri, Liqin Dong, Kinman Ng, Humphrey Zhao, Danbi Shin 신단비, Sang Don Yoon.
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