Rachit G. work email
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Rachit G. personal email
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With a Masters degree in Computer Engineering and a Bachelors in Electrical and Electronics Engineering, I also have a strong technical experience of working on Digital Design/verification in various roles. Currently working on Data Center centric networking switches.Skills- Understanding micro-arch and design to come up with full verification strategy till coverage closure- Knowledge of Single-core and multi-core CPU architecture- Knowledge of UVM verification methodology for Design verification- Developing SV/C tests (for testing a block with an ARMV8-A low-power CPU) for a complex SoC- Setting up transactors for AXI/AHB/AMBA protocols in a UVM based verification environment- Env automation using perl/python scriptsProgramming/HDL's/HVLs : C/C++, PERL, Verilog, SV, UVMEDA Tools/Platforms : NCSim, VCS, ModelSim, Synopsys Design Compiler, DVE, Jasper Gold, Zebu/Palladium (testbench acceleration)
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Dv EngineerBroadcom Inc. Nov 2015 - PresentPalo Alto, California, UsWorking on custom ASIC networking chips primarily targeted at data centers -
Design Verification EngineerQualcomm Feb 2015 - Nov 2015San Diego, Ca, Us- UVM testbench development for block-level verification- Developed tests for both UVM based testing with transactors and C tests for testing a module with an ARM core- Developed automation scripts to minimize effect of SoC level changes on block level verification- Setup formal verification environment for bus certification of AHB and AXI interfaces- Worked on setting up AXI/AHB/AMBA4 transactors in a UVM environment -
Co-Op Soc VerificationQualcomm Sep 2014 - Dec 2014San Diego, Ca, Us- Development and support for verification of a multi-core SoC design on Cadence PXP hardware accelerator- Worked with coherence team to develop a Perl script to simplify debug process in a multi-core (ARM-V8) environment
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Interim Engineering Intern-Ip DevelopmentQualcomm May 2014 - Aug 2014San Diego, Ca, Us- Worked on chip-level integration of power management block; C & SV test development for • SPMI interface for chip power up and power down sequence in the supported power modes • Wake-up from external interrupts in various power modes- Worked with coherence team to develop a Perl script to simplify debug process in a multi-core environment- Performed tool evaluation of Synopsys X-prop; explored tool integration in current verification environment
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Engineer - Traction EngineeringBharat Heavy Electricals Limited Jul 2011 - Jul 2013New Delhi, Delhi, In• Instrumental in development & testing of embedded controller (using TI DSP and Altera CPLD) for a traction grade power converter; type-tested to meet IEC standards• Carried out power circuit & controller simulations in Matlab-Simulink for a novel design of IGBT based power converter; extensively tested the prototype converter to meet strict customer specifications• Worked closely with component manufacturers to meet packaging and power constraints of critical components• Documented and developed training and troubleshooting manuals for the end-user to understand the operation and service related aspects of the unique product -
Intern – Front-End Asic Verification EngineerLantiq Communications India Pvt. Ltd. Jan 2011 - Jun 2011Us• Developed test cases in C and verified integration of UART and SPI interfaces at chip level for a SoC• Assigned the task of project migration from ModelSim to Cadence NC Sim environment; made necessary modifications in RTL and wrote PERL scripts for automatic data porting into the new environment• Took up the task of SystemVerilog integration with the existing verification environment -
Senior Core MemberDepartment Of Art & Decoration, Bits Pilani May 2010 - May 2011
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HeadDepartment Of Art & Decoration, Bits Pilani May 2010 - Dec 2010• Worked with a diverse student group engaged in creating works of art giving a unique theme to the campus• Handled inventory management for all the student organizations involved in major cultural and technical events
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Core MemberDepartment Of Art & Decoration, Bits Pilani May 2009 - May 2010
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Member - Working CommitteeStudents Council For Cultural Activities, Bits Pilani Jan 2010 - Dec 2010• Successfully organized an international level cultural festival; one among 6 member planning and execution committee
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Technical Trainee/Summer InternNational Thermal Power Station May 2009 - Jul 2009New Delhi, In- Carried out a case study for SCADA (Supervisory Control and Data Acquisition) system installation on existing units of the power plant; worked out probable logistic issues and project implementation costs -
MemberMarketing Club, Bits Pilani Jan 2008 - May 2008
Rachit G. Education Details
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North Carolina State UniversityComputer Engineering -
Birla Institute Of Technology And Science, PilaniElectrical & Electronics
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Sachdeva Public School,RohiniScience
Frequently Asked Questions about Rachit G.
What company does Rachit G. work for?
Rachit G. works for Broadcom Inc.
What is Rachit G.'s role at the current company?
Rachit G.'s current role is DV Engineer.
What is Rachit G.'s email address?
Rachit G.'s email address is ra****@****ail.com
What schools did Rachit G. attend?
Rachit G. attended North Carolina State University, Birla Institute Of Technology And Science, Pilani, Sachdeva Public School,rohini.
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