Radhakrishnan K.R Email & Phone Number

Coimbatore, Tamil Nadu, India

Teaching and Research

Coimbatore Area, India

Bengaluru Area, India

Bengaluru, Karnataka, India

During my internship period, I am working under Mr. Gautam Doshi, Architect, Senior Principal Engineer in Idea 2 Realty Group, Intel Technology India Pvt Ltd, Bangalore. The aim of the project was to evaluate Power, Performance and Area Analysis (PPA) of various open RISC V cores. My contribution in this project was configuring different instruction sets supporting RISCV Tool chain, different simulations and emulation platforms for various open cores. I have used different benchmarks to verify… Show more During my internship period, I am working under Mr. Gautam Doshi, Architect, Senior Principal Engineer in Idea 2 Realty Group, Intel Technology India Pvt Ltd, Bangalore. The aim of the project was to evaluate Power, Performance and Area Analysis (PPA) of various open RISC V cores. My contribution in this project was configuring different instruction sets supporting RISCV Tool chain, different simulations and emulation platforms for various open cores. I have used different benchmarks to verify the performance of the CPU. I am working on different FPGA boards to verify functional verification and also estimate the resources of various cores. I have used Synopsys design compiler/Cadence SOC Encounter for physical design flow (RTL to GDSII ) for various RISC V cores to observe the power and area of the cores. During this internship, in the front-end, I have mainly worked with Bluespec Verilog to generate synthesizable Verilog code. I have contributed to the Back-end/Physical-Design of the RiseCreek test-chip (22nm) and also working closely with IIT Madras RiseCreek Team, Intel Custom Foundry & HCL Team. The kind of knowledge that I gained during my internship could be used in both front-end and back-end design flow. I worked in the latest cutting-edge technologies available in the core industry. With the world evolving so fast it has become mandatory for every individual to get exposed to the emerging concepts and techniques. A right mentor is essential to achieve this. My aim is to work towards a RISC V Back end PDK flow in the semiconductor industry.Experience has taught me how to build strong relationships with all Teams at an organization. I have the ability to work within a team as well as cross-team. I can work with SoC Design, Verification engineers to resolve technical issues and implement technical enhancements, work with the development team to implement design and functional enhancements, and optimization. Show less

Bengaluru, Karnataka, India

During my internship period, I am working under Mr. Gautam Doshi, Architect, Senior Principal Engineer in Idea 2 Realty Group, Intel , Bangalore. The aim of the project was to evaluate Power, Performance and Area Analysis (PPA) of various open RISC V cores. My contribution in this project was configuring different instruction sets supporting RISCV Tool chain, different simulations and emulation platforms for various open cores. I have used different benchmarks (Dhrystone, coremark, Free RTOS… Show more During my internship period, I am working under Mr. Gautam Doshi, Architect, Senior Principal Engineer in Idea 2 Realty Group, Intel , Bangalore. The aim of the project was to evaluate Power, Performance and Area Analysis (PPA) of various open RISC V cores. My contribution in this project was configuring different instruction sets supporting RISCV Tool chain, different simulations and emulation platforms for various open cores. I have used different benchmarks (Dhrystone, coremark, Free RTOS, and Zephyr RTOS, etc.) to verify the performance of the CPU. I am working on different FPGA boards to verify functional verification and also estimate the resources of various cores. I have used Synopsys design compiler/Cadence SOC Encounter for physical design flow (RTL to GDSII ) for various RISC V cores to observe the power and area of the cores. During this internship, in the front-end, I have mainly worked with Bluespec Verilog to generate synthesizable Verilog code. I have contributed to the Back-end/Physical-Design of the RiseCreek test-chip (22nm) and also working closely with IIT Madras RiseCreek Team, Intel Custom Foundry & HCL Team.The kind of knowledge that I gained during my internship could be used in both front-end and back-end design flow. I worked in the latest cutting-edge technologies available in the core industry. With the world evolving so fast it has become mandatory for every individual to get exposed to the emerging concepts and techniques. My aim is to work towards a Back end PDK flow in the semiconductor industry. Experience has taught me how to build strong relationships with all Teams at an organization. I have the ability to work within a team as well as cross-team. I can work with SoC Design, Verification engineers to resolve technical issues and implement technical enhancements, work with the development team to implement design and functional enhancements, and optimization. Show less

Doctor Of Philosophy - Phd, Vlsi Architectures For Signal Processing Applications

Master’S Degree, Vlsi Design, 8.52

Activities and Societies: Class Representative & Placement Representative

B.E, Electronics And Communication Engineering