Experience and Specialties: Excellent at design chip micro-architecture of compute and data compression, such as mixed-precision and sparsity of GEMM engine for general AI accelerators, provide WW1 PPA for general matrix and vector computation for all the sparse and dense vector/matrix scenarios covering CNN, GNN, transformer, and LLM applications.Familiar with python-based AI/deep learning/reinforcement learning platforms and library such as PyTorch, PyTorch Geometrics, Deep Graph Library. Experienced in Digital IC Design flow, includes Verilog HDL/VHDL programming, simulators NCSim/VCS, synthesis tool Design Compiler, STA tool, FPGA tools.