Raghav Khandelwal Email and Phone Number

- Worked as part of the Tegra SOC Verification team, responsible for full chip level verification and signoff- Handled top level modelling of design behaviour in Verilog and formal verification of a sub-IP in the SOC- Utilized SystemVerilog Assertions(SVA) to write constraints, checkers and cover points for RTL design- Developed test cases to handle cluster level verification of the sub-IP

- Designed a system to seamlessly integrate Internet of Things(IoT) devices with LLMs for embedded system development- Leveraged OpenAI GPT 4.0 model via API calls from the ESP32 for programming and debugging of MCUs - Developed system for seamless interfacing of sensors with MCUs with minimal technical knowledge and human intervention- Optimized the system for power and latency utilizing the ESP-SDK reducing power consumption by over 50%

- As part of the Physical Design team, evaluated the timing criticality of design for DL1 subsystem of a 5nm SoC chip- Enabled STA runs throughout the Placement, CTS and Routing stages and summarized critical data around timing performance - Analyzed the critical PVT corners for setup and hold slack violations on Tempus and Primetime Timing Signoff tools- Flagged TDRC violations in the design and wrote ECO cycle for MPW fixes to provide feedback to physical design leads

-Designed a Long Range(LoRa) based Wireless Sensor Network for precision agriculture applications-Interfaced commercially available agricultural sensors and automatic weather station with ESP32 based microcontroller-Redirected all the sensor data from the end devices in small packets to The Things Network (TTN) cloud via LoRaWAN gateway-Worked on devising a Time Division Multiplexing Algorithm(TDMA) to avoid clashes between the data streams

- Worked on development of a farm monitoring system that measured parameters like soil moisture- Interfaced commercial sensors with Arduino microcontroller through RS 485 communication device using MODBUS protocol