Raghav Chaudhary Email and Phone Number
Objective: To work with commitment and efficiency to grow with the organization.Specialties: 1. FPGA Prototyping.2. Simulation Acceleration.3. Verilog/C/C++4. Perl/Make/TCL/Assembly.5. Problem Solving and Analytics.
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Software EngineerSynopsys Inc Nov 2024 - PresentNoida, Uttar Pradesh, India -
Software EngineerCadence Design Systems Jul 2022 - Oct 2024Noida, Uttar Pradesh, India -
Software ConsultantReal Intent May 2021 - Jun 2022Noida, Uttar Pradesh, India -
Principal Software EngineerCadence Design Systems Jul 2019 - May 2021Noida Area, India -
Lead Software EngineerCadence Design Systems Jun 2017 - Jun 2019Noida Area, India -
Lead Member Of Technical StaffMentor Graphics Aug 2015 - Jun 2017NoidaProduct: FPGA Based Prototyping:Projects: Runtime System for FPGA Prototyping:a. Create User Interface.b. Inter Process Communication.c. Integrating third Part Librariesd. Board File Generator:e. Automated the flow for Design partioning.f. Displaying the results in an HTML/XLS Format -
Senior Member Technical StaffMentor Graphics Apr 2013 - Jul 2015Noida Area, IndiaProduct: Simulation Accelerator:Projects:1. Creating the front end of the Product for the user interaction in TCL with Auto Completion and History maintenance with the help of TECLA Library. Implementation of Dictionary: Ternary Search Tree for storing the words.2. Wrote the Debug infrastructure for setting up the HW breakpoints of our Custom Logic Processor, helps in examining the HW registers and their states. Some of the commands are similar to GDB(step,cont/info,etc).3. Created Debug/Production and Assertion Builds and its Infrastructure. Productization of the S/W according to the different generated builds.4. Created the Non-Recursive Make Build Infrastructure in our Product.5. Worked on Verification of the IP of the HW Accelerator in System Verilog.6. Multi-Process Communication through File I/O Layer, where File Read/Write is responsible for communication between two processes.7. Wave form Generation for the simulator. Creating a messaging System in the S/W to curb/allow messages to print.8. Signal Trapping, where S/W creates its own Stack Trace in case of SEGFAULT. HANDLING SIG_INT and check/poll the state of the S/W and H/W and then resume with the Flow.9. Support For Regression Infrastructure.10. C++ Trainer for the New Joinees -
Software Engineer - IMediatek Jul 2011 - Mar 2013Noida Area, India- Experience of working on Multiple Binary Architecture and Dynamic RAM usage.- Experience of regional language engine like BIDI, ICU and proprietary engines for Indian, Arabic and south east languages.- Working on bitmap font engine- Experience of working on mobile editor and IME.- Experience of working on RTOS (Nucleus Plus) and mobile processors like ARM7/ARM9.- Proficiency at various levels of product development from requirement gathering, requirement analysis, design, development, system testing and documentation.- Strong analytical, programming and debug skills.
Raghav Chaudhary Education Details
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Dr. B. R. Ambdkar Natonal Institute Of Technology, JalandharComputer Science -
Svkm80.1 -
St Anne'S High School86
Frequently Asked Questions about Raghav Chaudhary
What company does Raghav Chaudhary work for?
Raghav Chaudhary works for Synopsys Inc
What is Raghav Chaudhary's role at the current company?
Raghav Chaudhary's current role is Software Engineer.
What schools did Raghav Chaudhary attend?
Raghav Chaudhary attended Dr. B. R. Ambdkar Natonal Institute Of Technology, Jalandhar, Svkm, St Anne's High School.
Who are Raghav Chaudhary's colleagues?
Raghav Chaudhary's colleagues are Zhengfan Xia, Kui Zhang, Siranush Sargsyan, Megha U, Bharat Singh, Suman B Patil, Kazuhiko Takaya.
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