Raghavendra H R Email and Phone Number

As a physical design engineer trainee, I dive into the intricate world of semiconductor chip design. My days are filled with learning the fundamentals of layout design, understanding design rules, and mastering CAD tools such as IC-Compiler, IC Validator, Star RC and Prime Time essential for chip development. Under the guidance of experienced mentors, I immerse myself in the process of translating circuit schematics into physical layouts through flow from floorplanning, STA, Placement and routing CTS, DRC to signoff , ensuring optimal performance and manufacturability.