Raghu Pasupuleti Email & Phone Number

Telangana, India

Bengaluru, Karnataka, India

Bengaluru, Karnataka, India

I'm responsible for floor planning, power planning, placement, routing, and conducting signoff checks (DRC, LVS, etc.) for both analog and digital cells.

Bengaluru, Karnataka, India

DOMAIN EXPERTISE : Generating Analysis report on all signoff flows and Health Checks. Layout convergence done using all the PV flows (DRC, LVS, Density, Latchup, Antenna, HealthChecks and Intel specific flows) for SoC partitions on ICC2. Worked on all Health checks: clock_shield_missing vias,pcab_errors, pg_connectivity_error,power_grid_missing_vias, cb2_extrashpes,pmj errors (sanity check) . Worked on signoff flows: online_lvs (shorts,opens,floatings) , denallIP, dfi_integra, drcds,trclvs(hierarchicalshorts), trcopens (RF opens), Trcshorts,sdgchill,drcipall,hip_erc,drc_SEL(signoff flows). Worked on antenna violations by adding a diode & layer hopping. Timing/RV ECOs implemented (Buffer additions, Upsize, Downsize, adding PG vias andimproving the power mesh) Fixed all DRC errors from base layers to uppermost metal layers including isolation and viacoloring related errors. Faced challenges while doing diffusion contact related edits, cell movements/swapping/flipwithassociated signal reroutings and reroutings in congested FILL DB Extraction_pv implemented: worked on opens and shorts which are dumped in extraction reports Xor2spec implemented: fixed all missing vias and nets & extra shapes of nets and vias.All edits are done on FILL & Pre-Fill DBs which is challenging in ICC2 tool.Analyzed and Worked on Trappers by Loading Oasis (IC Workbench)

Hyderabad, Telangana, India

• Profound knowledge on CMOS fundamentals, short channel effects, and digital electronics• Familiar with flows such as synthesis flow, PNR flow (Floorplan, Placement, CTS, Routing, ECO, PNR outputs ) and concepts related to STA• ALU, ORCA, PCI designs are implemented as part of training• Completed Industry Oriented training in ASIC Physical Design, Logic Synthesis and Static Timing• Analysis at 28nm and 32nm technology nodes.• Worked on various block-level implementations from Netlist to GDSII.• Expertise in ASIC flow, Logic Synthesis, Physical Design flow, ECO fixing, and Timing closure.• Performed Static Timing Analysis for multiple PVT corners, modes & scenarios.• Good scripting knowledge -TCL, and UNIX Shell Scripting.• EDA tools: Design Compiler, Synopsys IC Compiler II

Bachelor Of Technology - Btech, Electronics And Communications Engineering, First Class With Distinction

Intermediate, Mpc, First Class

Ssc, First Class