Rahul Dev Email & Phone Number

Santa Clara, California, US

Santa Clara, California, US

• Worked on implementation/verification of debug bus system involving DSMs( Debug State Machine), cross trigger logic and other blocks used for debugging system behavior during chip bringup, performance analysis, system.
• Patent filed( coauthored), granted by USPTO on design of Debugbus circuit in power aware scenario.
• Several spotlight awards.
• Worked on Verification of IP blocks( Such as ATI Auxiliary Test Interface, LARR Latch arrays, Fuse Interface) used in several generations of APU,GPU, CPU product lines including APU for Xbox One.
• Wrote C++ model/ Parser to be used in verification/ chip bringing up and production of ATI feature – Auxiliary Test Interface to bring in high volume data to run at speed system level test during wafer sort, catch.
• Write System Verilog UVM model to verify FUSE interface logic (Supply data used for BIST engine launch in SMS Star Memory System & LARR Latch Arrays) as well as hard repair on memories.

US

Responsibilities -Design and Development of multimillion gate home networking chip. 1.Implementation of behavioral models( using C language) of several sub-blocks to be used for Preamble Detection, Impulse Response Estimate, Data Capture, Maximum Energy window, FFT Averaging.2.Testplan and Test bench development for FDF( Front End Digital Filter) block.

Burlington, Massachusetts, US

ASIC Design( Sub blocks in a DSL digital filter design), Functional Verification/Formal Verification/ DFT-ATPG/Memory BIST1. Specification and Design of a fully programmable AFE Interface Block used in a multi-million gate DSL chip design.2. Design, Verification of a Memory Bist Engine(using a MARCH algorithm) to be used on a Multi-million gate SOC.3..

1. Verification of XGMII downshifter protocol for a Storage Area Networking Device-Understanding of XGMII protocol, 10 Gigabit Ethernet MAC (IEEE 802.3ae).-Developed the test plan document.-Developed verification environment in VERA, developed VERA tasks for stream generation and checking.-Verified the DUT by running test cases.2. Verification of the PCI.

Geneva, Switzerland, CH

1. Design,verification and synthesis of PCI slave module: --Study of the PCI 2.x specifications.-Designed and RTL coded the PCI module as per the specifications.-Integrated the slave module with the host and ran cycles exercising this block. -Synthesized the slave module using synopsys DC and achieved timing 2. Design,verification,synthesis and prototyping.