Rahul Dev Email & Phone Number

Santa Clara, California, Us

Santa Clara, California, Us

• Worked on implementation/verification of debug bus system involving DSMs( Debug State Machine), cross trigger logic and other blocks used for debugging system behavior during chip bringup, performance analysis, system hang etc.• Patent filed( coauthored), granted by USPTO on design of Debugbus circuit in power aware scenario.• Several spotlight awards.• Worked on Verification of IP blocks( Such as ATI Auxiliary Test Interface, LARR Latch arrays, Fuse Interface) used in several generations of APU,GPU, CPU product lines including APU for Xbox One.• Wrote C++ model/ Parser to be used in verification/ chip bringing up and production of ATI feature – Auxiliary Test Interface to bring in high volume data to run at speed system level test during wafer sort, catch problems early, reduce buildout/packaging costs.• Write System Verilog UVM model to verify FUSE interface logic (Supply data used for BIST engine launch in SMS Star Memory System & LARR Latch Arrays) as well as hard repair on memories.• Familiarity with power aware scenarios, voltage islands, power gating, clock gating, familiarity with Security on ASICS

Us

Responsibilities -Design and Development of multimillion gate home networking chip. 1.Implementation of behavioral models( using C language) of several sub-blocks to be used for Preamble Detection, Impulse Response Estimate, Data Capture, Maximum Energy window, FFT Averaging.2.Testplan and Test bench development for FDF( Front End Digital Filter) block using System Verilog. Development of Interfaces, Drivers/BFMs, Scoreboards etc. AVM, constrained-random testbenches used.3.Formal Verification (both RTl-to-gates and gate-to-gate) on several cores. 4. Gate Level Simulations( Back-annotated using FAST and SLOW SDFs).5. Test pattern development ( to be used in production test program)

Burlington, Massachusetts, Us

ASIC Design( Sub blocks in a DSL digital filter design), Functional Verification/Formal Verification/ DFT-ATPG/Memory BIST1. Specification and Design of a fully programmable AFE Interface Block used in a multi-million gate DSL chip design.2. Design, Verification of a Memory Bist Engine(using a MARCH algorithm) to be used on a Multi-million gate SOC.3. Implementation of Tx Interpolation/ Rx Decimation LPF filters to be used in AFE Interface to be used in a DSL/VDSL chip.4.Verification of several modules( including but not limited to Vargain/Window, FDF) using C based coverification environment.5.Formal Verification (both RTl-to-gates and gate-to-gate) of generations of DSL/VDSL Chip Designs.6. ATPG on several generations of DSL/VDSL chips. Used TETRAMAX tool from Synopsys for obtaining/debugging scan coverage.

1. Verification of XGMII downshifter protocol for a Storage Area Networking Device-Understanding of XGMII protocol, 10 Gigabit Ethernet MAC (IEEE 802.3ae).-Developed the test plan document.-Developed verification environment in VERA, developed VERA tasks for stream generation and checking.-Verified the DUT by running test cases.2. Verification of the PCI I/f in system controller -Study of the functional specification and the test plan document for the PCI controller core.-Study of the VERA/verilog test environment involving tasks and functions used for cycle generation and checking.-Ran simulations with the previously written test cases. Analysis of the failing/hanging test cases (previously written according to the test plan document) and filing of the bug report (s) .-Recoding the test cases (VERA test bench) covering all the areas as in the test plan document.

Geneva, Switzerland, Ch

1. Design ,verification and synthesis of PCI slave module: --Study of the PCI 2.x specifications.-Designed and RTL coded the PCI module as per the specifications.-Integrated the slave module with the host and ran cycles exercising this block. -Synthesized the slave module using synopsys DC and achieved timing 2. Design ,verification ,synthesis and prototyping of HOST/PCI bridge (North bridge) -Study of the Pentium(x86) bus interface and the BFM for generating cycles. -Involved in architectural discussions and the block partitioning.-Designed, RTL coded the performance, configuration register, write posting as well as read prefetch buffers.Integrated the various modules to generate the system top. -Developed the test plan document. -Developed test cases in ‘C’ and ran them.-Traced bugs and helped fixing them.-Compiled the HOST design for XILINX FPGA virtex E 2000 using FPGA Compiler II and generated files appropriate for prototyping using the Aptix system explorer FPCB (field programmable circuit board, Hardware). -Involved in the prototype setup and booting of DOS/ windows on the setup.3.Design of behavioral model of L2 cache controller and integration with HOST-Designed and developed the L2 cache controller module used for the debugging of the HOST/PCI bridge and L2 interface. -Integrated it with the HOST and ran tests pertaining to cache operations. -Found bugs and fixed them.4. Design and implementation of Protel netlist to verilog netlist Converter-Designed and developed the C based program which converts the PCB netlist into verilog top level file.-Tested using a sample netlist from the board development team.