Rahul Raveendran Email and Phone Number
Rahul Raveendran work email
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Rahul Raveendran personal email
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Experienced VLSI Engineer with a demonstrated history of working in the Semiconductor Industry. Skilled in System Verilog, Verilog, VHDL, UVM, Python, Perl, Microsoft Word, C, ASIC and SOC Design and Front-end Implementation, ASIC/SOC verification and debugging. Completed MSc. in Embedded Electronics Engineering from Lund University, Sweden.
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Asic Digital Design Engineer , StaffSynopsys Inc May 2022 - PresentSunnyvale, California, Us -
Asic Developer - Asic Design And Asic VerificationAcconeer Ab Jun 2021 - May 2022Malmö, Skåne County, Se -
Master Thesis StudentAcconeer Ab Jan 2021 - May 2021Malmö, Skåne County, SeCustomization of Ibex RISC-V Processor Core -
Asic DeveloperAcconeer Ab Sep 2020 - Oct 2020Malmö, Skåne County, Se -
Asic DeveloperAcconeer Ab Jun 2020 - Aug 2020Malmö, Skåne County, Se -
Asic DeveloperAcconeer Ab Dec 2019 - May 2020Malmö, Skåne County, Se -
Vlsi Engineer - Asic & Soc VerificationWipro Limited Apr 2017 - Aug 2019Bangalore, Karnataka, In
Rahul Raveendran Skills
Rahul Raveendran Education Details
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Lund UniversityEmbedded Electronics Engineering -
Royal College Of Engg & Technology, AkkikavuElectronics And Communication Engineering -
Govt.Janatha Higher Secondary SchoolComputer Science -
Mannam Memmorial High SchoolHigh School
Frequently Asked Questions about Rahul Raveendran
What company does Rahul Raveendran work for?
Rahul Raveendran works for Synopsys Inc
What is Rahul Raveendran's role at the current company?
Rahul Raveendran's current role is ASIC/SOC Design & Front-end Implementation Engineer.
What is Rahul Raveendran's email address?
Rahul Raveendran's email address is ra****@****ail.com
What schools did Rahul Raveendran attend?
Rahul Raveendran attended Lund University, Royal College Of Engg & Technology, Akkikavu, Govt.janatha Higher Secondary School, Mannam Memmorial High School.
What skills is Rahul Raveendran known for?
Rahul Raveendran has skills like Leadership, Ahb5, Proteus, Cadence Virtuoso, System On A Chip, Linux, Apb, Xilinx Vivado, Debugging, Gate Level Simulation, Windows, Very Large Scale Integration.
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