Rahul Suram Email & Phone Number

Having 1.5 year experience as Synthesis and STA Engineer on various cutting edge lower technology nodes (6nm, 4nm, 3nm) of TSMC for MediaTek SoCs. Good understating about the entire flow of RTL-to-GDSII.Responsible for UPF based Power Aware Physical Synthesis and Implementation ( logical cell place/opt and Pre-CTS ), Formal Verification, Scan Insertion, ATPG pattern generation and coverage analysis,Conformal Low Power Check, PreSTA, QC checks for mobile SoCs chipsets.Worked closely with Physical Design Team, providing optimal solutions for Congestion analysis.Also have experience in FloorPlanning, Place and Route, DRC, LVS, ECO fixes.