Who is Raj P.? Overview
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Quick answer
Raj P. is listed as Founder and CEO at AllyIn.ai, based in San Jose, California, United States. AeroLeads shows a work email signal at cadence.com and a matched LinkedIn profile for Raj P..
Raj P. previously worked as Arch/Perf Tech Lead & Manager at Meta and Co-founder and Core Committee Member at Emc^2: An Ml/Ai Workshop. Raj P. holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from University Of Rochester.
Company email context
Email format at AllyIn.ai
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*@cadence.com
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Profile bio
About Raj P.
Research Interests: AI/ML Accelerator Architectures, Intelligent System Design, Processor microarchitecture, SIMD Design, Memory subsystem design, Network-on-chipSkills: Architectural exploration, Performance modeling and simulation, Pathfinding and Feasibility Analysis, PPA Analysis, Workload profiling, Compiler analysis and optimization
Listed skills include Computer Architecture, Vhdl, Simulations, C, and 23 others.
Current workplace
Raj P.'s current company
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16 roles
Raj P. work experience
A career timeline built from the work history available for this profile.
Arch/Perf Tech Lead & Manager
CurrentInfra Silicon (ML ASIC) and MTIA Ref: https://ai.facebook.com/blog/meta-training-inference-accelerator-AI-MTIA/
Oct 2022 - Present
Co-Founder And Core Committee Member
Current
Emc^2: An Ml/Ai Workshop
https://www.emc2-ai.org/9th edition: ASPLOS 20248th edition: AAAI 20237th edition: Virtual Solo Event 20216th edition: Virtual Solo Event 20205th edition: NIPS 20194th edition: ISCA 20193rd edition: CVPR 20192nd edition: HPCA 20191st edition: ASPLOS 2018
Jan 2018 - Present
Chief Ai Architect
- Architectural definition of current and future products- Feasibility studies and perf/power projections, End-to-end workload PPA analysis- Performance modeling and architectural exploration (SIMD, NoC, Compute)- HW software co-design, vector processing and performance tuning- SoC and system architecture, Performance verification and correlation- ML software (middle and backend): ISA def, mapper, partitioner, schedulerRef: d-Matrix Corsair https://www.forbes.com/sites/karlfreund/2022/06/21/d-matrix-ai-chip-promises-efficient-transformer-processing/
Apr 2021 - Sep 2022
Sr. Performance Architect
Silicon Engineering Solutions (SES)Worked on large scale future gen ML/AI training systems for NLP workloads, SIMD HW-SW Co-designRef: Microsoft Athena — https://www.tomshardware.com/news/microsoft-athena-ai-chip-tsmc
Oct 2019 - Apr 2021
Sr. Principal Design Engineer
Lead performance architect for DNA 100 v2.0 AI processor.
Jun 2019 - Oct 2019
Principal Design Engineer
Tensilica IP R&D Group: Lead performance architect of Tensilica’s first gen DNA 100 AI processor. Architectural exploration, performance modeling and microarchitectural analysis Xtensa Vision DSPs; performance correlation and modeling of DSP memory subsystems and prefetching mechanisms
Aug 2016 - Jun 2019
Cpu Performance Microarchitect
Lead performance architect of P series Warrior cores P5600 and P6600. Also worked on I-series core codename Samurai (I6400)
Jan 2014 - Aug 2016
Research Assistant
Advanced Computer Architecture LabSingle thread performance improvement using decoupled look-ahead techniques and self-tuning.Best paper award ISMM 2016
Aug 2008 - Jul 2016
Teaching Assistant
Multiprocessor design, High-Performance Microprocessor based Systems, Advanced Computer Architecture, Computer Organization, Electronics Devices and Circuits
Sep 2008 - Nov 2011
May 2012 - Aug 2012
Jan 2008 - Jul 2008
Jun 2006 - Jan 2008
Professional Assistant
Advanced Digitial VLSI Design, Oysters (VLSI design) Lab
Jan 2006 - Jun 2006
Jul 2005 - Dec 2005
Jun 2004 - Aug 2004
3 education records
Raj P. education
Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering
University Of Rochester
Ms, Electrical And Compter Engineering
University Of Rochester
B.E.(Hons.), Electrical & Electronics Engineering
Birla Institute Of Technology And Science, Pilani
FAQ
Frequently asked questions about Raj P.
Quick answers generated from the profile data available on this page.
What company does Raj P. work for?
Raj P. works for AllyIn.ai.
What is Raj P.'s role at AllyIn.ai?
Raj P. is listed as Founder and CEO at AllyIn.ai.
What is Raj P.'s email address?
AeroLeads has found 1 work email signal at @cadence.com for Raj P. at AllyIn.ai.
Where is Raj P. based?
Raj P. is based in San Jose, California, United States while working with AllyIn.ai.
What companies has Raj P. worked for?
Raj P. has worked for Allyin.Ai, Meta, Emc^2: An Ml/Ai Workshop, D-Matrix Corporation, and Microsoft.
How can I contact Raj P.?
You can use AeroLeads to view verified contact signals for Raj P. at AllyIn.ai, including work email, phone, and LinkedIn data when available.
What schools did Raj P. attend?
Raj P. holds Doctor Of Philosophy (Ph.D.), Electrical And Computer Engineering from University Of Rochester.
What skills is Raj P. known for?
Raj P. is listed with skills including Computer Architecture, Vhdl, Simulations, C, Vlsi, Microprocessors, Embedded Systems, and C++.
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