Raj P. work email
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Raj P. personal email
Research Interests: AI/ML Accelerator Architectures, Intelligent System Design, Processor microarchitecture, SIMD Design, Memory subsystem design, Network-on-chipSkills: Architectural exploration, Performance modeling and simulation, Pathfinding and Feasibility Analysis, PPA Analysis, Workload profiling, Compiler analysis and optimization
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Founder And CeoAllyin.AiSan Jose, Ca, Us -
Arch/Perf Tech Lead & ManagerMeta Oct 2022 - PresentMenlo Park, Ca, UsInfra Silicon (ML ASIC) and MTIA Ref: https://ai.facebook.com/blog/meta-training-inference-accelerator-AI-MTIA/ -
Co-Founder And Core Committee MemberEmc^2: An Ml/Ai Workshop Jan 2018 - Presenthttps://www.emc2-ai.org/9th edition: ASPLOS 20248th edition: AAAI 20237th edition: Virtual Solo Event 20216th edition: Virtual Solo Event 20205th edition: NIPS 20194th edition: ISCA 20193rd edition: CVPR 20192nd edition: HPCA 20191st edition: ASPLOS 2018
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Chief Ai ArchitectD-Matrix Corporation Apr 2021 - Sep 2022Santa Clara, California, Us- Architectural definition of current and future products- Feasibility studies and perf/power projections, End-to-end workload PPA analysis- Performance modeling and architectural exploration (SIMD, NoC, Compute)- HW software co-design, vector processing and performance tuning- SoC and system architecture, Performance verification and correlation- ML software (middle and backend): ISA def, mapper, partitioner, schedulerRef: d-Matrix Corsair https://www.forbes.com/sites/karlfreund/2022/06/21/d-matrix-ai-chip-promises-efficient-transformer-processing/ -
Sr. Performance ArchitectMicrosoft Oct 2019 - Apr 2021Redmond, Washington, UsSilicon Engineering Solutions (SES)Worked on large scale future gen ML/AI training systems for NLP workloads, SIMD HW-SW Co-designRef: Microsoft Athena — https://www.tomshardware.com/news/microsoft-athena-ai-chip-tsmc -
Sr. Principal Design EngineerCadence Design Systems Jun 2019 - Oct 2019San Jose, California, UsLead performance architect for DNA 100 v2.0 AI processor. -
Principal Design EngineerCadence Design Systems Aug 2016 - Jun 2019San Jose, California, UsTensilica IP R&D Group: Lead performance architect of Tensilica’s first gen DNA 100 AI processor. Architectural exploration, performance modeling and microarchitectural analysis Xtensa Vision DSPs; performance correlation and modeling of DSP memory subsystems and prefetching mechanisms
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Cpu Performance MicroarchitectImagination Technologies Jan 2014 - Aug 2016Kings Langley, Hertfordshire, GbLead performance architect of P series Warrior cores P5600 and P6600. Also worked on I-series core codename Samurai (I6400) -
Research AssistantUniversity Of Rochester Aug 2008 - Jul 2016Rochester, Ny, UsAdvanced Computer Architecture LabSingle thread performance improvement using decoupled look-ahead techniques and self-tuning.Best paper award ISMM 2016 -
Teaching AssistantUniversity Of Rochester Sep 2008 - Nov 2011Rochester, Ny, UsMultiprocessor design, High-Performance Microprocessor based Systems, Advanced Computer Architecture, Computer Organization, Electronics Devices and Circuits
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Summer InternIbm Research Almaden May 2012 - Aug 2012Armonk, New York, Ny, UsContent Protection Group -
Technical Marketing EngineerCypress Semiconductor Jan 2008 - Jul 2008San Jose, Ca, UsPower PSoC Group -
Applications EngineerMicrochip Technology Jun 2006 - Jan 2008Chandler, Az, UsAdvanced Microcontroller Architecture Division -
Professional AssistantBirla Institute Of Technology And Science Pilani Jan 2006 - Jun 2006Jhunjhunu, Rajasthan, InAdvanced Digitial VLSI Design, Oysters (VLSI design) Lab -
Research InternMicrosoft Research India Jul 2005 - Dec 2005Redmond, Washington, UsTrends in Emerging Market Group
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Summer InternCsir-Ceeri Jun 2004 - Aug 2004Pilani, Rajasthan, InVLSI Group
Raj P. Skills
Raj P. Education Details
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University Of RochesterElectrical And Computer Engineering -
University Of RochesterElectrical And Compter Engineering
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Birla Institute Of Technology And Science, PilaniElectrical & Electronics Engineering
Frequently Asked Questions about Raj P.
What company does Raj P. work for?
Raj P. works for Allyin.ai
What is Raj P.'s role at the current company?
Raj P.'s current role is Founder and CEO.
What is Raj P.'s email address?
Raj P.'s email address is rp****@****nce.com
What schools did Raj P. attend?
Raj P. attended University Of Rochester, University Of Rochester, Birla Institute Of Technology And Science, Pilani.
What are some of Raj P.'s interests?
Raj P. has interest in Outdoor Activities, Education, Hiking, Sports, Science And Technology, Human Rights.
What skills is Raj P. known for?
Raj P. has skills like Computer Architecture, Vhdl, Simulations, C, Vlsi, Microprocessors, Embedded Systems, C++, Matlab, Verilog, Fpga, Algorithms.
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