Rajanish "Raj" Donthi (Rajanish.Donthi@Gmail.Com) Email & Phone Number

Folsom, California, United States

Sacramento, California Area

Validate power management features of integrated graphics core.in R&D group

• Designed FPGA logic to integrate customized IO interfaces, timing and triggering features for IO and other unique features includes synchronization with GPS-disciplined clock and temperature safe system turn-off.• Implemented FPGA design as a Xilinx ISE project with module coded with VHDL, Synthesized, Simulated with ModelSim and Verified the functionality and Timing• Integrated IP core also tested and debugged hardware using JTAG and host tools.

• Developed Low power ASIC design flow and tool methodology utilizing ARM 90nm technology libraries• RTL-to-Gates Synthesis of RISC design using Design compiler with timing constraints• Implemented Floorplan, Placement, Clock Tree Synthesis (CTS) & Routing of RISC Design using IC compiler• Automated design implementation using Tcl scripts and Makefiles• Organized and documented project database to efficiently track libraries, procedures and related documents

• Implemented Matching Pursuit Algorithm: Simulation Approach for Machine Fault Detection• Successfully developed DSP algorithm in MATLAB using advanced techniques of Wavelet Transform.• Detected and illustrated (3D) the exact location of Faulty Parameters from the given Machine Test signals.

M.S., Electrical Engineering

Activities and Societies: IEEE student chapter Some of Major Projects in area of ASIC, FPGA, Embedded system are given below Design.

M.S, Electrical Engineering

Activities and Societies: IEEE, Sanskar

Education record

Education record

Activities and Societies: SNUG