Rajan Paudel Email and Phone Number
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Seasoned Semiconductor Product Engineering Director with over 17+ years of Semiconductor Product Engineering experience. Leading extremely passionate engineering team focused on innovative and result driven Engineering work which will lead to cost-effective technical solutions for overall product optimization while taking from Design to Mass Production.Broad-based experiences in designing different testflow in order to weed out the infant failures and establishing the grading solution for a products which can meet high endurance/performance for enterprise SSDs quality products on advanced 3D NAND. Recommended multiple system level testing and on the fly solutions for client solid state drives(SSDs) and enterprise solid state drives(SSDs), which helped to ramp the products ahead of schedule.Trained the global team regarding predicting the high endurance/high performance capability of a die based on time 0 manufacturing testing.15+ approved/pending patents with Sandisk Corp.Specialties:Driving highly experienced Engineers to provide overall innovative product solutions.Expertise on taking advanced 3D NAND from Design to high volume by working with different groups such as design, device, fab, production and system team.Strong understating of 3D Advanced NAND defects and its screening methodology + defect management at system level.Expert on designing a test flow and low cost testing methodologies for 3D Advance NAND flash.Hands on working experience on resolving customer issues on timely manner by quick collaboration with multiple teams.
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Director Of Product EngineeringWestern Digital Mar 2019 - PresentSan Jose, Ca, Us
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Senior Technologist Product EngineerWestern Digital Oct 2018 - Feb 2019San Jose, Ca, Us
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Technologist Product EngineerWestern Digital Oct 2016 - Sep 2018San Jose, Ca, Us
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Senior Staff Product EngineerSandisk, A Western Digital Brand Feb 2015 - Oct 2016Milpitas, Ca, Us -
Staff Product EngineerSandisk, A Western Digital Brand Dec 2013 - Feb 2015Milpitas, Ca, Us• Worked on industry smallest 2D NAND Flash Node of 15nm with rocket cell structure• Established the effective and robust working flow for wafer testing and overall memory testing with very competitive testing cost• Worked very close with Designers to understand the potential fail mode early in the life cycle of product in order to avoid issues during ramp and to avoid any customer returns• With this model was able to successfully launch this memory on different platform such as embedded, client SSD, Enterprise SSDs with least no of customer return in the entire company• Strong involvement during qualifying process of one of the critical client SSD product with none system level solution yet meet the very tight DPPM criteria, which helped to gain the client SSD retail market share with very competitive profit margin• Worked closely with Enterprise SSD team on qualifying the memory with OEM customers based on their strict DPPM/Endurance criteria
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Senior Product EngineerMicron Technology Mar 2012 - Dec 2013Boise, Idaho, Us Pre silicon verification through simulation on 3D NAND FLASH Debugging the new 3D NAND challenges from Design and Process prospect. Working closely with design on optimizing the Charge Pump and regulators by minimizing the leakage path. Strong involvement in developing the new Probe test methodologies and implementation on Probe with minimal Probe test time. Cross collaboration with yield Engineers on doing electrical failure analysis to facilitate their physical failure analysis. Working with Intel Engineers on wafer level debug including string conductivity on 3D strings, cell level characterization (cycling, data retention) -
Lead Product EngineerMicron Technology May 2010 - Mar 2012Boise, Idaho, Us Probe support lead for multiple 20nm/30nm process SLC and MLC NAND designs with main focus being developing Probe test screens/stresses for higher yield and generating reliable materials. Worked closely with Probe and PE management to meet and exceed test time on Probe, schedules and resolve technical issues. Leadership responsibilities include helping and navigating the product throughout the product life cycle which include design, process integration, cell development, reliability, probe, assembly, backend and quality assurance. My group was actively involved in establishing screens and stresses on wafer and package level and coming up with new test methodologies for the tight spec (such as TPROG,TBERS,TR) of Mobile applications.
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Product EngineerMicron Technology Feb 2006 - May 2010Boise, Idaho, Us• Worked on multiple projects in MLC and SLC NAND Flash.• Primary Probe PE support for the first Micron/Intel 50nm 300mm wafer ramp in Virginia Micron Fab • Job responsibility constitutes working with probe test group to understand and analyze root cause for a wafer level yield loss and coordinate with process integration team to optimize yield.• Experienced in wafer level debug with expertise in circuit level validation and electrical micro-probing skills on Nextest Maverick series testers. Resolved critical issues during initial silicon phase• Pre silicon activities include block level and full chip simulations using HSIM, and Verilog simulators to validate new design features, device functionality and datasheet specs.• Responsible for Probe/Backend production support developing test flows, correlating different testing platforms, test time reduction, monitoring and improving Probe/Backend yields.• Worked on reproducing and debugging probe, backend fails on bench tester and propose screens and design edits to fix them to drive higher Yield on Probe and backend.• Interacted with customers through RMA group to understand their quality requirements and debug the customer returns through electrical-physical failure analysis and proposed screens at Probe/Backend.• Adept at analyzing the characterization data using statistical software tools such as Yield3 and JMP to make accurate inferences and come up with appropriate parameter settings for the device.
Rajan Paudel Skills
Rajan Paudel Education Details
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University Of ArizonaElectrical And Electronics Engineering
Frequently Asked Questions about Rajan Paudel
What company does Rajan Paudel work for?
Rajan Paudel works for Western Digital
What is Rajan Paudel's role at the current company?
Rajan Paudel's current role is Director of Product Design Engineering at WD, a Western Digital Company.
What is Rajan Paudel's email address?
Rajan Paudel's email address is rp****@****ail.com
What is Rajan Paudel's direct phone number?
Rajan Paudel's direct phone number is +140821*****
What schools did Rajan Paudel attend?
Rajan Paudel attended University Of Arizona.
What skills is Rajan Paudel known for?
Rajan Paudel has skills like Product Engineering, Testing, Failure Analysis, Debugging, Yield, Semiconductors, Manufacturing, Engineering, Verilog, Microsoft Office, Customer Service, Microsoft Excel.
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