Rajath Umesh Joshi Email & Phone Number

Santa Clara, Ca, Us

Santa Clara, California, Us

Santa Clara, California, Us

Santa Clara, California, Us

Responsibilities as an intern in the High Performance Computing Group included Verilog and SystemVerilog RTL design of sub-blocks for various IPs.Performed lint checks on the sub-blocks using SpyGlass Lint and cleaned up lint violations by making RTL edits.Carried out Clock Domain Crossing checks on IPs using SpyGlass CDC, debugged and rectified Clock Domain Crossing issues.Debugged and fixed tool issues pertaining to SpyGlass Lint and SpyGlass CDC.

Santa Clara, California, Us

I was part of IACG (Intel Architecture Core Group) which is responsible for designing next-generation Intel Microprocessors that drive Servers, Laptops and Desktops. My team was involved in the design of Microprocessor Cores. I designed Datapath as well as RLS Functional Unit Blocks (FUBs) pertaining to the execution cluster. I was responsible for the complete backend design of FUBs ranging from Synthesis to Layout Design and Verification. My work involved Logic Synthesis, Logic Optimization, Power Optimization, Floorplanning, Partitioning, Power Planning, Placement, Timing driven Placement Optimization, Clock Tree Synthesis, Routing, Signal Integrity Analysis, Timing Closure, Layout Verification and Reliability Verification. I have worked on multiple projects based on 14nm and 10nm microarchitecture.

Master'S Degree, Computer Engineering

Bachelor Of Engineering - Be, Electrical, Electronics And Communications Engineering