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Rajesh Goel is listed as Senior Director Of Engineering - Chipset PE at Qualcomm, based in San Diego, California, United States. AeroLeads shows a work email signal at qualcomm.com and a matched LinkedIn profile for Rajesh Goel.
Rajesh Goel previously worked as Senior Director, Engineering at Qualcomm and VLSI Design Manager at Spike Technologies. Rajesh Goel holds Be, Electronics And Communications from Delhi College Of Engineering.
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Current Role: Mobile chipset PE; Engineering Lead for Snapdragon mobile chipset. Complete end to end responsible for product spec definition to execution(both HW and SW), commercialization, and support.Past:- Dynamic and enterprising executive with extensive hands-on experience in design verification for Qualcomm's Adreno GPUs, Multi-media IPs, Sub-systems and Snapdragon SoCs.- Successful functional, performance, and power verification of 50+ Adreno GPUs across 4 generations for mobile handset market.- Commercialize first of its generation Adreno GPU with first silicon in every generation.- Envisioned and fostered industry leading innovations in a wide range of domains:- Constrained Random coverage driven Verification using System Verilog (OVM, UVM) and formal for Graphics(OpenGL, OpenCL, DX, Vulkan), Video(MPEG-2/4, h.263/264/265(HEVC), VC1, VP6/7/8), Camera(MIPI-CSI, ISP, JPEG), Audio(MIDI)- Simulation acceleration using veloce and FPGAs for HW-SW/FW pre-silicon co-verification, and use-case analysis to help reduce time to market.- Built an elite global team of 100+ engineers for verification of IPs, sub-system and SoCs.- On schedule delivery of high-quality multi-media Ips, Sub-systems, and SoCs for handset and tablet market.
Listed skills include Verilog, Soc, Systemverilog, Vlsi, and 17 others.
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San Diego, Ca, Us
Engineering Lead for Snapdragon mobile chipset. Complete end to end responsible for product spec definition to execution(both HW and SW), commercialization, and support.
San Diego, Ca, Us
Founded multi-media design verification team and now leading Adreno GPU verification.Strategy and planning-Developed the process for pre-silicon functional, performance, and power verification of multi-media IPs for handsets.-Set-up process and methodology for coverage driven constrained random verification with SystemVerilog(OVM -> UVM), formal, Hector, and coverage convergence.-Set-up formal procedures of verification milestones reviews for completeness and work closely with team on efficiency/quality improvement initiatives/automations.Execution-Participate in design architecture, test-planning, testbench architecture, functional coverage, test development, debug, and coverage closure.-Responsible for delivery of 10-12 designs every year and a new architecture every couple of years. Able to commercialize first of its generation GPU with first Silicon in every generation. -Also responsible for emulation, simulation acceleration using veloce, and simulation with all 3 popular simulators.Innovations-Enabled team on simaccel for power and performance verification in concurrent system-level use-case context pre-silicon.-Came-up with a unique solution for SW development and validation on HW pre-silicon, helps in reducing time to market and an improved HW/SW quality. -Closed loop verification: Architected state of the art tool to generate coverage model from test-plan and annotates the plan based on coverage results.-Automatic test development tool.Business-Work closely with EDA vendors, CAD, IT, methodology, VIP, licenses, finance, suppliers, staffing, and equipment teams for budgeting, forecasting, and improvements in efficiency and quality.Team/leadership:-Hiring, grooming, and leading a team of highly talented engineers.-Developed a distinguished team of ~100 design verification engineers for Graphics and more for other multi-media designs.Successful verification and tapeout of multiple SOCs as verification lead, for mobile devices. (04-06)
Us
Worked on customer (Fujitsu, Cisco, Velio, Photuris, LSI-Logic, Xilinx, IKOS, iWatt) projects in design verification and complete silicon flow from RTL to GDSII.Successfully verified designs for networking (layer 2 and 3 switches) in constrained random and directed random verification with Vera, C++, and Verilog.Delivered high quality GDSII for customer designs with entire execution team in Bangalore office.Single point of contact for customer during planning and execution of the projects.
Us
Worked on memory modeling, simulator evaluation, and BFM verification for processor i960rp.
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Rajesh Goel works for Qualcomm.
Rajesh Goel is listed as Senior Director Of Engineering - Chipset PE at Qualcomm.
AeroLeads has found 1 work email signal at @qualcomm.com for Rajesh Goel at Qualcomm.
Rajesh Goel is based in San Diego, California, United States while working with Qualcomm.
Rajesh Goel has worked for Qualcomm and Spike Technologies.
You can use AeroLeads to view verified contact signals for Rajesh Goel at Qualcomm, including work email, phone, and LinkedIn data when available.
Rajesh Goel holds Be, Electronics And Communications from Delhi College Of Engineering.
Rajesh Goel is listed with skills including Verilog, Soc, Systemverilog, Vlsi, Rtl Design, Functional Verification, Asic, and Debugging.
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