Rajesh Kedia Email and Phone Number
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Rajesh Kedia is a Assistant Professor at IIT Hyderabad at Department of CSE, IIT Hyderabad. He possess expertise in soc, dft, verilog, chip architecture, formal verification and 12 more skills. Colleagues describe him as "This guy used to be one of the talented guys of my undergrad batch. He is a hardcore programmer. I had learnt a lot from him in terms of programming tricks or electronics fundamentals. Always hardworking and takes his work seriouly. No doubt would love to work with him in the future and he will definitely be an asset to any organization." and "Rajesh Kedia has been a gem of a student throughout his career. My association with him dates back to Pre-University college days. He was then as much a diligent student as he was in his engineering days. A techie to the core coupled with excellent reasoning and analytic power and he is a great teacher of his choice of subjects. Innovative thinking is his forte and perseverance is his way of life. Nice to have such a long relationship with you and definitely looking forward for a lasting one."
Department Of Cse, Iit Hyderabad
View- Employees:
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Assistant ProfessorDepartment Of Cse, Iit Hyderabad Dec 2021 - PresentKandi, Telangana, IndiaAssistant Professor - teaching, research, and research! -
Principal Project ScientistIndian Institute Of Technology, Delhi Jul 2020 - Dec 2021New Delhi, Delhi, IndiaWorked with Prof. Preeti Ranjan Panda on various research activities related to thermal management of computer systems and modeling of caches. -
Lead EngineerTexas Instruments India Pvt. Ltd. Jul 2012 - Dec 2014Bengaluru, Karnataka, IndiaOwned embedded software development (bootcode development) for a complex chip taking care of multiple requirements.Mentored some of the new team members to get them upto speed on work.Setup the gate level simulations and supported the team to cleanup about 5000 testcases for a completely new technology based chip. -
Senior Design EngineerTexas Instruments India Pvt. Ltd. Feb 2010 - Jul 2012Bengaluru Area, IndiaFront-end digital engineer working on various aspects of digital design. Recent experience involves contributions in SoC verification for a complex technology driver chip. Defined the SoC verification environment and the verification strategy.Mentored some of the new team members to get them upto speed on work. -
Design EngineerTexas Instruments India Pvt. Ltd. Jul 2006 - Feb 2010Primary contributions & experience in the verification and DFT domains.Defined the scan strategy for a completely new family of devices which has never used scan. Worked with people across continents and got the optimal implementation between power and testability.Owned SoC verification for various modules and system scenarios. Developed good understanding of JTAG, ADC, WDT, SoC memory map hookup, verification environment, test coding care-abouts etc.Owned toplevel integration for 2 different microcontroller devices and no integration bugs found so-far.Implemented various automation techniques and improved productivity of self and team.
Rajesh Kedia Skills
Rajesh Kedia Education Details
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Computer Science And Engineering -
Electronics And Communication Engineering -
Ravenshaw Junior College, CuttackScience -
Joharimall High School, CuttackSecondary
Frequently Asked Questions about Rajesh Kedia
What company does Rajesh Kedia work for?
Rajesh Kedia works for Department Of Cse, Iit Hyderabad
What is Rajesh Kedia's role at the current company?
Rajesh Kedia's current role is Assistant Professor at IIT Hyderabad.
What is Rajesh Kedia's email address?
Rajesh Kedia's email address is ke****@****ail.com
What schools did Rajesh Kedia attend?
Rajesh Kedia attended Indian Institute Of Technology, Delhi, Malaviya National Institute Of Technology Jaipur, Ravenshaw Junior College, Cuttack, Joharimall High School, Cuttack.
What are some of Rajesh Kedia's interests?
Rajesh Kedia has interest in Talks, Formal Verification, Automation, System Architecture, Tech.
What skills is Rajesh Kedia known for?
Rajesh Kedia has skills like Soc, Dft, Verilog, Chip Architecture, Formal Verification, Functional Verification, Gate Level Simulation, Embedded C, Embedded Software, Microcontrollers, Vlsi, Asic.
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Rajesh Kedia
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