Rajesh Saha

Rajesh Saha Email and Phone Number

Senior Member of Technical Staff at AMD @ AMD
santa clara, california, united states
Rajesh Saha's Location
Bengaluru, Karnataka, India, India
Rajesh Saha's Contact Details

Rajesh Saha work email

Rajesh Saha personal email

About Rajesh Saha

Rajesh Saha is a Senior Member of Technical Staff at AMD at AMD. He possess expertise in physical design, spice, signal integrity, static timing analysis, place and route and 5 more skills. Colleagues describe him as "Rajesh is a high energy, enthusiastic and tenacious engineer. Never frightened to take on new problems knowing that it will expand his knowledge and experience. Great team player, contributing directly or indirectly, whether he owns the task and listening to suggestions from other members of the team or is helping a team member and contributing ideas and thoughts into the mix. A joy to work with and appreciate his methodical approach." and "I'd the pleasure to work with Rajesh during my time at AMD and found Rajesh to be a very detailed oriented and positive individual who cares deeply and takes a lot of pride in the quality of work which he consistently delivered. Rajesh is very knowledgeable in the area of EMIR which is his passion and ensured that we taped out the complex SOC without comprising on the EMIR aspect of the chip."

Rajesh Saha's Current Company Details
AMD

Amd

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Senior Member of Technical Staff at AMD
santa clara, california, united states
Website:
amd.com
Employees:
16705
Rajesh Saha Work Experience Details
  • Amd
    Senior Member Of Technical Staff
    Amd Jul 2015 - Present
    Bengaluru Area, India
  • Amd
    Member Of Technical Staff
    Amd May 2012 - Present
    Bengaluru Area, India
    * Power integrity analysis and signoff for x86 processors/discrete GPU/semi-custom processors* Power integrity methodology development* Power integrity runtime and accuracy improvement * Yield improvement at sort - ScanIRConference Presentations:1. AMD Asia Technical Conference (AATC2013) - "Electrical reusable View approach for on-chip cdie computation"2. AMD Asia Technical Conference (AATC2014) - "ScanIR for PDN robustness and yield recovery"3. Ansys… Show more * Power integrity analysis and signoff for x86 processors/discrete GPU/semi-custom processors* Power integrity methodology development* Power integrity runtime and accuracy improvement * Yield improvement at sort - ScanIRConference Presentations:1. AMD Asia Technical Conference (AATC2013) - "Electrical reusable View approach for on-chip cdie computation"2. AMD Asia Technical Conference (AATC2014) - "ScanIR for PDN robustness and yield recovery"3. Ansys Electronics Simulation Expo - "ScanIR for PDN robustness and yield recovery" Show less
  • Amd
    Senior Design Engineer
    Amd Sep 2008 - Apr 2012
    Bengaluru Area, India
    * Logic implementation for channel blocks* Custom netlist creation, custom placement and custom routing* Source Synchronous Bus (SSB) implementation and timing closure* Fullchip power integrity analysis for server soc* Power integrity analysis for core with package plane for gated domain
  • Capricorn Career Incubation
    Founder
    Capricorn Career Incubation Aug 2008 - Mar 2012
    Mandya Area, India
    VLSI school to help Engineering & MTech students of Mandya. Taught the following subjects* VLSI fundamentals* Unix and shell scripting* Perl scripting* GNU plot
  • Montalvo Systems
    Design Engineer - Iii
    Montalvo Systems Mar 2007 - Sep 2008
    Bengaluru Area, India
    * Memory controller datapath implementation* Custom RTL to Gate implementation using verilog* PnR and timing closure
  • Intel Technologies
    Component Design Engineer
    Intel Technologies 2002 - 2006
    Bengaluru Area, India
    Responsible for Power Estimation, Power Reduction and Power Delivery on 32bit xeon processor design.
  • Ibm Microelectronics
    Physical Design Engineer
    Ibm Microelectronics 2000 - 2002
    Bengaluru Area, India
    Floorplanning, PnR, clock tree synthesis, clock tree balancing, Power Delivery
  • St-Iisc Research Labs
    Project Assistant
    St-Iisc Research Labs 1999 - 2000
    Bengaluru Area, India
    Spice Mocromodeling for PWM circuit for 180nm technology node

Rajesh Saha Skills

Physical Design Spice Signal Integrity Static Timing Analysis Place And Route Power Integrity Analysis And Design Debug Esd Analysis Die Package Co Simulation Rampup Analysis For Power Gated Design Power Grid Design And Implementation

Rajesh Saha Education Details

Frequently Asked Questions about Rajesh Saha

What company does Rajesh Saha work for?

Rajesh Saha works for Amd

What is Rajesh Saha's role at the current company?

Rajesh Saha's current role is Senior Member of Technical Staff at AMD.

What is Rajesh Saha's email address?

Rajesh Saha's email address is sa****@****hoo.com

What schools did Rajesh Saha attend?

Rajesh Saha attended Manipal University, University Of Mysore, Ucla Extension.

What skills is Rajesh Saha known for?

Rajesh Saha has skills like Physical Design, Spice, Signal Integrity, Static Timing Analysis, Place And Route, Power Integrity Analysis And Design Debug, Esd Analysis, Die Package Co Simulation, Rampup Analysis For Power Gated Design, Power Grid Design And Implementation.

Who are Rajesh Saha's colleagues?

Rajesh Saha's colleagues are Sbusiso Ncube, Leo Reyes, Ramasidda Gadadi, Wade Lintz, Ding Feng, Biping Wu, Can Turk.

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