AeroLeads people directory · profile
Rakesh K. Email & Phone Number
Staff SoC Performance Architect
at
Google
1 work email found
@google.com
LinkedIn matched
✓ Verified Jul 2026
4 data sources
Profile completeness 100%
Current company
Role
Staff SoC Performance Architect
Location
San Francisco Bay Area, United States
Company size
Who is Rakesh K.? Overview
A concise factual answer block for searchers comparing this professional profile.
Quick answer
Rakesh K. is listed as Staff SoC Performance Architect at Google, a with 315106 employees, based in San Francisco Bay Area, United States. AeroLeads shows a work email signal at google.com and a matched LinkedIn profile for Rakesh K..
Rakesh K. previously worked as Sr. SoC Performance Architect at Google and Hardware Engineer at Apple. Rakesh K. holds Doctor Of Philosophy (Phd), Electrical Engineering from Massachusetts Institute Of Technology.
Company email context
Email format at Google
This section adds company-level context without repeating Rakesh K.'s masked contact details.
{first}.{last}@google.com
86% confidence
AeroLeads found 1 current-domain work email signal for Rakesh K.. Compare company email patterns before reaching out.
Profile bio
About Rakesh K.
Rakesh K. is a Staff SoC Performance Architect at Google. He possess expertise in fpga, algorithms, digital signal processors, labview, matlab and 9 more skills.
Listed skills include Fpga, Algorithms, Digital Signal Processors, Labview, and 10 others.
Current workplace
Rakesh K.'s current company
Company context helps verify the profile and gives searchers a useful next step.
Google
17 roles
Rakesh K. work experience
A career timeline built from the work history available for this profile.
Role listed
Sr. Soc Performance Architect
Hardware Engineer
Jul 2019 - Jul 2022
Graduate Research Assistant
Led Tata Center funded project on elongating lifetimes of lead acid batteries in rural micro-grids and solar home systems.- Designed and built an inexpensive battery monitoring platform for deployment in rural environments- Analyzed effects of depth of discharge (DoD), temperature, and charge/discharge rates on lead acid battery cycle life- Leveraged machine learning to perform predictive analysis of battery state of charge (SoC) and state of health (SoH)
Oct 2017 - Jun 2019
Graduate Teaching Assistant
Graduate TA for 6.004 - Intro to Computation Structures- Introductory course on architecture of digital systems. Starting with MOS transistors, the course introduces a series of building blocks to eventually build a simple RISC based computerResponsibilities:- Led weekly recitations to reinforce lecture material- Held office hours so students can seek help on assignments or address general questions- Collaborated with other TAs to help design, administer, and grade course exams
Feb 2016 - Dec 2017
President Of Consulting Club At Mit (Ccm)
- Directed one of MIT’s largest student groups: 15-person board / 1,500 members- Oversaw 5 executive teams that delivered 30+ events to over 350 attendees- Coordinated with industry mentors to connect members to consulting opportunities
Dec 2016 - Nov 2017
Engagement Manager - Volunteer Consulting Group
- Launched engagement with big data consulting startup from Harvard Innovation Labs- Identified 7 Fortune 100 companies and 8 university partners for Series A financing- Developed 2 year growth strategy for improved client acquisition and retention
Jan 2017 - Mar 2017
Vice President Of Consulting Club At Mit (Ccm)
- Led CCM weekly case practice events - Collaborated with Harvard Graduate Consulting Club (HGCC) to plan and host the 2016 Harvard vs MIT Case Competition- Led the effort to secure various funding sources for 2016 Harvard / MIT case competition
Feb 2016 - Dec 2016
Graduate Student Researcher
- Developed MEMS and PCB scale probe head for nanoscale imaging under Dr. Jeffrey Lang - Designed and fabricated microstructures in MIT’s Microsystem Technology Lab - Designed low noise, high frequency circuitry to be able to detect changes in sensor I/V relationship- Proficient with different lab equipment such as oscilloscopes, power supplies, high frequency signal generators, impedance analyzers, and vector network analyzers (VNAs)
Sep 2014 - Aug 2016
Management Consultant
- Associate on a 6 member consultant team to provide optimal customer acquisition strategies for local hotelier - Conducted 23 staff and customer interviews to identify key weak points in client’s business
Dec 2015 - Feb 2016
Power Validation Engineering Intern
- Created novel IVD analysis tool to study impact of power grid droop on timing accuracy- Collaborated with Platform Architecture team to refine trace based flow for power analysis- Worked with power modeling team to improve workload models using silicon measurements
May 2018 - Aug 2018
Soc Power Integrity Intern
- Created analysis and automation flows to reduce SoC IVD by 20-25%- Developed IVD aware timing analysis methodology to improve STA accuracy- Presented novel photo search algorithm to Sr. management as intern contest finalist
May 2017 - Aug 2017
Physical Design Engineering Intern
-Aided POWER9 methodology team to develop new concurrent subsystem checks-Designed optimal wire tapering algorithms to minimize RC delay to meet slack/skew targets-Developed optimal pin placement scripts for POWER9 bus control unit
Jun 2015 - Aug 2015
Logic Design Engineering Intern
-Helped logic design team add new functionality to next generation of QDSP cores-Worked with physical design, low power, and DFT teams to refine QDSP RTL -Restructured RTL library to allow for synthesis of multiple QDSP generations on a single chip
May 2014 - Aug 2014
Digital Design Lab Lead Teaching Assistant
-Head TA in lab course on Rapid Prototyping and FPGA Design-Instructed students on use of lab equipment and CADET Design board
Jan 2013 - Apr 2014
Low Power Engineering Intern
-Generated power vs. bandwidth models of QDSP system network on chip -Implemented power prediction algorithms for QDSP benchmarks to aid in PD efforts -Designed mapping system for RTL macros for quicker, more accurate power analysis
May 2013 - Aug 2013
3 education records
Rakesh K. education
Doctor Of Philosophy (Phd), Electrical Engineering
Massachusetts Institute Of Technology
Master Of Science (M.S.), Electrical Engineering
Massachusetts Institute Of Technology
B.S, Electrical Engineering
Georgia Institute Of Technology
FAQ
Frequently asked questions about Rakesh K.
Quick answers generated from the profile data available on this page.
What company does Rakesh K. work for?
Rakesh K. works for Google.
What is Rakesh K.'s role at Google?
Rakesh K. is listed as Staff SoC Performance Architect at Google.
What is Rakesh K.'s email address?
AeroLeads has found 1 work email signal at @google.com for Rakesh K. at Google.
Where is Rakesh K. based?
Rakesh K. is based in San Francisco Bay Area, United States while working with Google.
What companies has Rakesh K. worked for?
Rakesh K. has worked for Google, Apple, Massachusetts Institute Of Technology, Ibm, and Qualcomm.
How can I contact Rakesh K.?
You can use AeroLeads to view verified contact signals for Rakesh K. at Google, including work email, phone, and LinkedIn data when available.
What schools did Rakesh K. attend?
Rakesh K. holds Doctor Of Philosophy (Phd), Electrical Engineering from Massachusetts Institute Of Technology.
What skills is Rakesh K. known for?
Rakesh K. is listed with skills including Fpga, Algorithms, Digital Signal Processors, Labview, Matlab, C, Microsoft Office, and C++.
Find 750M verified contacts
Search by job title, company, industry, location, and seniority. Export verified B2B contact data when you need it.
Start free trial