Rakesh K. Email and Phone Number
California, United States
Rakesh K.'s Location
San Francisco Bay Area, United States, United States
Rakesh K.'s Contact Details
Rakesh K. work email
- Valid
- Valid
Rakesh K. personal email
n/a
About Rakesh K.
Rakesh K. is a Sr. SoC Performance Architect at Google at Google. He possess expertise in fpga, algorithms, digital signal processors, labview, matlab and 9 more skills.
Rakesh K.'s Current Company Details
Sr. SoC Performance Architect at Google
California, United States
- Website:
- goo.gle/3DLEokh
- Employees:
- 315106
- Company phone:
- 916.253.7820
Rakesh K. Work Experience Details
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GoogleCalifornia, United States
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Sr. Soc Performance ArchitectGoogle Jul 2022 - PresentMountain View, Ca, Us
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Hardware EngineerApple Jul 2019 - Jul 2022Cupertino, California, Us -
Graduate Research AssistantMassachusetts Institute Of Technology Oct 2017 - Jun 2019Cambridge, Ma, UsLed Tata Center funded project on elongating lifetimes of lead acid batteries in rural micro-grids and solar home systems.- Designed and built an inexpensive battery monitoring platform for deployment in rural environments- Analyzed effects of depth of discharge (DoD), temperature, and charge/discharge rates on lead acid battery cycle life- Leveraged machine learning to perform predictive analysis of battery state of charge (SoC) and state of health (SoH) -
Graduate Teaching AssistantMassachusetts Institute Of Technology Feb 2016 - Dec 2017Cambridge, Ma, UsGraduate TA for 6.004 - Intro to Computation Structures- Introductory course on architecture of digital systems. Starting with MOS transistors, the course introduces a series of building blocks to eventually build a simple RISC based computerResponsibilities:- Led weekly recitations to reinforce lecture material- Held office hours so students can seek help on assignments or address general questions- Collaborated with other TAs to help design, administer, and grade course exams
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President Of Consulting Club At Mit (Ccm)Massachusetts Institute Of Technology Dec 2016 - Nov 2017Cambridge, Ma, Us- Directed one of MIT’s largest student groups: 15-person board / 1,500 members- Oversaw 5 executive teams that delivered 30+ events to over 350 attendees- Coordinated with industry mentors to connect members to consulting opportunities
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Engagement Manager - Volunteer Consulting GroupMassachusetts Institute Of Technology Jan 2017 - Mar 2017Cambridge, Ma, Us- Launched engagement with big data consulting startup from Harvard Innovation Labs- Identified 7 Fortune 100 companies and 8 university partners for Series A financing- Developed 2 year growth strategy for improved client acquisition and retention
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Vice President Of Consulting Club At Mit (Ccm)Massachusetts Institute Of Technology Feb 2016 - Dec 2016Cambridge, Ma, Us- Led CCM weekly case practice events - Collaborated with Harvard Graduate Consulting Club (HGCC) to plan and host the 2016 Harvard vs MIT Case Competition- Led the effort to secure various funding sources for 2016 Harvard / MIT case competition
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Graduate Student ResearcherMassachusetts Institute Of Technology Sep 2014 - Aug 2016Cambridge, Ma, Us- Developed MEMS and PCB scale probe head for nanoscale imaging under Dr. Jeffrey Lang - Designed and fabricated microstructures in MIT’s Microsystem Technology Lab - Designed low noise, high frequency circuitry to be able to detect changes in sensor I/V relationship- Proficient with different lab equipment such as oscilloscopes, power supplies, high frequency signal generators, impedance analyzers, and vector network analyzers (VNAs)
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Management ConsultantMassachusetts Institute Of Technology Dec 2015 - Feb 2016Cambridge, Ma, Us- Associate on a 6 member consultant team to provide optimal customer acquisition strategies for local hotelier - Conducted 23 staff and customer interviews to identify key weak points in client’s business
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Power Validation Engineering InternApple May 2018 - Aug 2018Cupertino, California, Us- Created novel IVD analysis tool to study impact of power grid droop on timing accuracy- Collaborated with Platform Architecture team to refine trace based flow for power analysis- Worked with power modeling team to improve workload models using silicon measurements
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Soc Power Integrity InternApple May 2017 - Aug 2017Cupertino, California, Us- Created analysis and automation flows to reduce SoC IVD by 20-25%- Developed IVD aware timing analysis methodology to improve STA accuracy- Presented novel photo search algorithm to Sr. management as intern contest finalist
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Physical Design Engineering InternIbm Jun 2015 - Aug 2015Armonk, New York, Ny, Us-Aided POWER9 methodology team to develop new concurrent subsystem checks-Designed optimal wire tapering algorithms to minimize RC delay to meet slack/skew targets-Developed optimal pin placement scripts for POWER9 bus control unit -
Logic Design Engineering InternQualcomm May 2014 - Aug 2014San Diego, Ca, Us-Helped logic design team add new functionality to next generation of QDSP cores-Worked with physical design, low power, and DFT teams to refine QDSP RTL -Restructured RTL library to allow for synthesis of multiple QDSP generations on a single chip -
Digital Design Lab Lead Teaching AssistantGeorgia Institute Of Technology Jan 2013 - Apr 2014Atlanta, Georgia , Us-Head TA in lab course on Rapid Prototyping and FPGA Design-Instructed students on use of lab equipment and CADET Design board -
Low Power Engineering InternQualcomm May 2013 - Aug 2013San Diego, Ca, Us-Generated power vs. bandwidth models of QDSP system network on chip -Implemented power prediction algorithms for QDSP benchmarks to aid in PD efforts -Designed mapping system for RTL macros for quicker, more accurate power analysis
Rakesh K. Skills
Fpga
Algorithms
Digital Signal Processors
Labview
Matlab
C
Microsoft Office
C++
Vhdl
Java
Rtl Design
Integrated Circuit Design
Python
Engineering
Rakesh K. Education Details
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Massachusetts Institute Of TechnologyElectrical Engineering -
Massachusetts Institute Of TechnologyElectrical Engineering
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Georgia Institute Of TechnologyElectrical Engineering
Frequently Asked Questions about Rakesh K.
What company does Rakesh K. work for?
Rakesh K. works for Google
What is Rakesh K.'s role at the current company?
Rakesh K.'s current role is Sr. SoC Performance Architect at Google.
What is Rakesh K.'s email address?
Rakesh K.'s email address is rk****@****mit.edu
What schools did Rakesh K. attend?
Rakesh K. attended Massachusetts Institute Of Technology, Massachusetts Institute Of Technology, Georgia Institute Of Technology.
What skills is Rakesh K. known for?
Rakesh K. has skills like Fpga, Algorithms, Digital Signal Processors, Labview, Matlab, C, Microsoft Office, C++, Vhdl, Java, Rtl Design, Integrated Circuit Design.
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