Graduate Engineering Trainee
CurrentDeveloped and verified RTL designs using Verilog for 45nm technology node projects, proficient in 90nm and 180nm processes.Conducted simulations with Cadence Xcelium and performed logical equivalence checking using Conformal, executed physical and logical synthesis tasks using Cadence Genus.Utilized Cadence tools for synthesis and optimization, emphasizing area and power constraints.Learnt about the chip design stages including floor planning, power planning, and Clock Tree Synthesis (CTS), performed Static Timing Analysis and Place & Route (PnR) tasks using Cadence Innovus.Utilized semiconductor physics, CMOS technology, Low power techniques concepts in practical project work.Gained Hands on experience in Vivado HLS for FPGA based prototyping and design validation.