Rakshith Ravishankar Email & Phone Number

Redmond, Washington, Us

Redmond, Washington, Us

>Working on building verification environments for FPGA & AI based hardware accelerators designs >Block and system level verification >Regression development ,maintenance and bug fixes .>develop Constraint random UVM based test environment at block and sub system level to exercise various portions of the design comprising of protocols like axi,pcie,ethernet,DDR,cxl >Develop Functional coverage modules to capture various holes in the design and improvise on it.>Scripting and automation to setup CAD tool flows within the verification environment >Work on generating the Bitstrem PDI for Xilinx-Versal ACAP FPGA device and doing bring ups and programming over JTAG.>Documentation , test plan development, creating block diagrams.

San Jose, California, Us

>Part of RD & Customer Engagement team for Cadence - Xcelium parallel logic simulator.>Involved in debugging RTL , UVM -Test bench issues for block and full chip SOC level>Validation and Debug of the Random/Constraint solver engine.>Maintaining sanity regression and running qualification tests to validate new tool features.>Performing root cause analysis of failing tests and adding automation to capture performance metrics.>Reproducing customer issues by writing SV-UVM based test cases.>Involved in developing and setting up verification methodologies and infrastructure.>Simulator Performance validation ,qualification and benchmarking with custom SoC.>Providing IEEE -1801 - Low power debug and support to customers from EDA software front.>Developing UVM TB components for In house testing of the simulator >Perform Data analytics, automated reporting for internal team and customer.

Vadodara, Gujarat, In

>Performed block level verification and developed UVM verification component for I2C protocol>Performed gate level simulation for various IPs within Altera Stratix-10 FPGA. >Ownership of FPGA test bench architecture and sanity regression maintenance to close coverage. >Experience with integrating VIPs like Ethernet100G, PCIe-Gen4, DDR4 into UVMF system test bench and verify the intended behavior of the system. >Performed failure analysis & coverage checks on the DUT to analyze various holes and provided fix to bump up the coverage. >Performed CDC analysis & verification with questa-cdc on the DUT to capture violations and provided fix for it. >Assisting Sr Verification engineers to review new design specifications and develop a full chip verification plan and review test cases. >Worked as team with application groups to define, develop ,architect ,verify and release IP blocks.

Santa Clara, Ca, Us

Aliso Viejo, Ca, Us

>Involved in full cycle ASIC design (Logical and Physical Synthesis) of 10GbaseT Cu Ethernet PHY-IC>Involved in development and Integration of C++ and MATLAB reference models in to the test bench.>Assisted senior design engineers in design schematic and RTL design of sub blocks of SERDES.>Involved in physical design (PnR) from netlist generation to final GDS for PLL block of 10GBaseT-Ethernet-PHY-IC at TSMC -16nm process node.>Participated in data setup, macro block partitioning, floor planning, clock & power distribution and congestion analysis.>Performed Physical Verification (DRC/LVS/ESD/LUP/IR-Drop) at the top level(.GDS) with Mentor-Calibre .>Developed TCL Scripts to perform PIN placement in the floor planning stage and modified calibre rule decks for marker cell- LUP detection.>Performed Static Timing Analysis for different timing paths of the design using Prime Time-SI and developed timing constraints for DDR3-PHY.>Evaluated & benchmarked study for area/timing/routability impact using 7 & 9 track library at 28nm process>UPF design by adding level shifters, isolation and retention registers for generating power optimized netlist>Actively participated in overall development of Loopback and Compliance of PHY layer in System Verilog including planning, documentation, and implementation of BFM, scenarios, test cases, checkers and functional coverage.>Post silicon support using Advantest93K ATE to ensure successful bring up and enhance yield learning>Designed Test Script automation for extracting area, power and timing details from the netlist files into an excel spreadsheet using Perl/TCL.

>Handling and Managing IEEE - CS club events.>Team Lead for the SoC design projects>Hosts and Leads the weekly meetings to discuss the status .

Fullerton, Ca, Us

Foster City, California, Us

>Developed in house test script automation using PERL and maintained a test database on SQL-Server>Designed and developed several customer specific requirements such as custom reports.>Lead and handled the Product deployment and getting it live with minimal down time.>Experience in Customer Interaction,Resource Plans, and Release Communications.>Experience in handing a Real time Production environment>Experience in managing Real time production database>Managed Sev1 production issues>Worked on automation development which helped creating automated reports>Experience in handling Code releases>Hands on experience in Custom report generation

Bangalore, Karnataka, In

Master'S Degree, Computer Engineering

Master'S Degree, Electrical And Electronics Engineering

Bachelor Of Engineering (B.E.), Electrical, Electronics And Communications Engineering