CPU Power LeadPower characterization using PTPX/Power Artist for various CPU cores for different CPU benchmarks.Driving Power convergence(Dynamic and Leakage) and optimization.PMIC Buck Planning for CPUSS Rails.Silicon Correlation for Power and Vmin.Driving Throttling mechanism's/configurations for CPUSS.Custom IP definition//configuration like memories, reg arrays for best PPA.Inrush Mitigation with Sleep Staggering.Head Switch sizing for Ron/Ioff.IPF/Vector ownership for IR analysis.New Vector Development for CPUSS use casesMemory Subsystem DesignL1 Load/Store cache subsystem design supporting load, store and evictions for mobile CPUShared L3 Data Cache subsystem

Apple CPU Cache Design

L3 Cache Design(TAG, DATA, Snoop Filter, LRU) for Server ProcessorsSER(Soft Error Rate) Reduction Methodology for Xeon processor Design on 14nm process TechnologyDesign of Tag SRAM array section for 2.5 MB 20way set associative L3 Cache for Xeon processor on 32nm process technology Circuit Design of Multi Port Register Files and Data Path blocks for Pentium M processor on 45nm process technology Micro Sequence and Instruction Decode section timing (STA) lead for Pentium M processor on 45nm process technology Silicon Debug for yield/speed path for Intel Core duo processor on 65nm process technology