Ramin Safaeian Email and Phone Number

Senior FPGA Design Engineer with over 12+ years of experience specializing in high-throughput RTL design and FPGA implementation. Proficient in Verilog, SystemVerilog, and VHDL, with a focus on wireless (5G/LTE/Wimax/OFDM/DVB-T/DVB-T2/DVB-S/DVB-S2) and wireline Gigabit Ethernet up to 800G protocols. Deep understanding of wireless communication channels, receivers, and transmitters, as well as digital communication system blocks. Extensive hands-on experience with Multigigabit GTM Transceiver up to 53.125 PAM4 and digital interface protocols including PCIe, I2C, SPI, and UART. Highly Skilled in analog interfaces such as ADC/DACs and proficient with Xilinx Versal Premium, UltraScale+, 7 Series, and Zynq platforms. Expertise includes Vivado, ModelSim, QuestaSim, synthesis, static timing analysis, and timing closure. Experienced in MATLAB, Python and TCL scripting, as well as working with oscilloscopes, spectrum analyzers, and RF signal generators. Proficient in revision control software such as Jira and Perforce. Additionally, an expert in C++ programming language with familiarity in machine learning algorithms and concepts.